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rej03b0128-0100z rev.1.00 nov 01, 2002 rev.1.00 nov 01, 2002 page 1 of 139 rej03b0128-0100z m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP sngle-chip 8-bit cmos microcomputer 1. description the m37150m6/m8/ma/mc/mf-xxxfp and M37150EFFP are single-chip microcomputers designed with cmos silicon gate tech- nology. they have an osd, data slicer, and i 2 c-bus interface, mak- ing them perfect for tv channel selection systems with a closed cap- tion decoder. the M37150EFFP has a built-in prom that can be written electrically. 2. features number of basic instructions .................................................... 71 memory size rom .............. 24k bytes (m37150m6-xxxfp) 32k bytes (m37150m8-xxxfp) 40k bytes (m37150ma-xxxfp) 48k bytes (m37150mc-xxxfp) 60k bytes (m37150mf-xxxfp, M37150EFFP) ram ............... 1024 bytes (m37150m6-xxxfp) 1 152 bytes (m37150m8-xxxfp) 1472 bytes (m37150ma-xxxfp, m37150mc-xxxfp) 2048 bytes (m37150mf-xxxfp, M37150EFFP) (*rom correction memory included) minimum instruction execution time ................................ 0.447 s (at 3.58 mhz oscillation frequency) ................................ 0.451 s (at 4.43 mhz oscillation frequency) power source voltage ................................................. 5 v 10 % subroutine nesting ............................................. 128 levels (max.) interrupts ....................................................... 17 types, 16 vectors 8-bit timers .................................................................................. 6 programmable i/o ports (ports p0, p1, p2, p3 0 , p3 1 ) ............. 25 serial i/o ............................................................ 8-bit ? 1 channel multi-master i 2 c-bus interface .............................. 1 (3 systems) a-d comparator (7-bit resolution) ................................ 8 channels pwm output circuit ......................................................... 8-bit ? 5 power dissipation in high-speed mode ......................................................... 165 mw (at v cc = 5.5v, fscin = 3.58 mhz, osd on, and data slicer on) in low-speed mode ......................................................... 0.33 mw (at v cc = 5.5v, 32 khz oscillation frequency) closed caption data slicer rom correction function ................................................ 2 vectors osd function display characters ................................... 32 characters ? 2 lines (3 lines or more can be displayed by software) kinds of characters ........................................................ 254 kinds (coloring unit) (per charactor unit) character display area ............................ cc mode: 16 ? 26 dots osd mode: 16 ? 20 dots kinds of character sizes ..................................... cc mode: 1 kind osd mode: 8 kinds kinds of character colors .................................. 8 colors (r, g, b) coloring unit ................... character, character background, raster display position horizontal: 128 levels vertical: 512 levels attribute ........................................................................................ cc mode: smooth italic, underline, flash, automatic solid space osd mode: border smoth roll-up window function 3. application tv with closed caption decoder
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 2 of 139 rej03b0128-0100z t able of contents 1. description ............................................................... 1 2. features .................................................................... 1 3. application ................................................................ 1 4. pin configuration .................................................. 3 5. functional block diagram ................................. 4 6. performance overview ....................................... 5 7. pin description ........................................................ 7 8. functional description ..................................... 12 8.1 central processing unit (cpu) .......... 12 8.2 memory ........................................................ 13 8.3 interrupts ................................................. 18 8.4 timers .......................................................... 23 8.5 serial i/o ..................................................... 27 8.6 multi-master i 2 c-bus interface ......... 30 8.7 pwm output function ............................ 43 8.8 a-d comparator ........................................ 47 8.9 rom correction function ................... 49 8.10 data slicer ............................................... 50 8.11 osd functions ........................................ 61 8.11.1 display position ................................. 66 8.11.2 dot size ............................................. 70 8.11.3 clock for osd .................................... 71 8.11.4 field determination display ............... 72 8.11.5 memory for osd ................................ 74 8.11.6 character color .................................. 78 8.11.7 character background color ............... 78 8.11.8 out signals ....................................... 79 8.11.9 attribute .............................................. 80 8.11.10 multiline display ............................... 85 8.11.11 automatic solid space function ....... 86 8.11.12 scan mode ....................................... 87 8.11.13 window function ............................. 87 8.11.14 osd output pin control ................... 89 8.11.15 raster coloring function ................. 90 8.12 software runaway detect function .... 92 8.13 reset circuit .......................................... 93 8.14 clock generating circuit ................. 94 8.15 auto-clear circuit ............................. 100 8.16 addressing mode ................................ 100 8.17 machine instructions ....................... 100 9. technical notes ................................................. 100 10. absolute maximum ratings ........................... 101 1 1. recommended operating conditions ....... 101 12. electric characteristics ............................ 102 13. a-d converter characteristics ................. 104 14. multi-master i 2 c-bus bus line characteristics ..... 104 15. prom programming method ......................... 105 16. data required for mask orders ................ 106 17. one time prom version M37150EFFP marking .............. 107 18. appendix ............................................................... 108 19. package outline ............................................... 139
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 3 of 139 rej03b0128-0100z 4. pin configuration fig. 4.1 pin configuration (top view) 1 16 1 1 1 2 13 14 15 5 6 7 8 9 1 0 2 3 4 1 7 18 19 20 2 1 4 2 27 3 2 3 1 30 29 28 3 8 3 7 3 6 3 5 3 4 3 3 4 1 4 0 3 9 2 6 25 24 23 2 2 p1 1 /scl1 p0 0 /pwm0 p0 1 /pwm1 p0 2 /pwm2 p0 3 /pwm3/ad1 p0 4 /pwm4/ad2 p0 5 /ad3 p0 6 /int2/ad4 p0 7 /int1 p2 0 /sclk/ad5 p2 1 /sout/ad6 p2 2 /sin/ad7 p2 3 /tim3 p2 4 /tim2 p2 5 /int3 p2 6 /x cin p2 7 /x cout cnv ss v ss p1 2 /scl2 p1 3 /sda1 p1 4 /sda2 p1 6 /ad8/tim2 p5 0 /h sync p5 1 /v sync p5 2 /b p5 3 /g p5 4 /r p5 5 /out clk cont /p1 0 p3 0 /sda3 p3 1 /scl3 p1 5 fscin reset cvin v hold v cc hlf filt m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP nc outline 42p2r * open 20-pin.
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 4 of 139 rej03b0128-0100z 5. functional block diagram fig. 5.1 functional block diagram of m37150 v c c v s s cnv ss x c i n x c o u t p0 (8) int1 int2 int 3 p1 (7) p w m 4 p w m 3 p w m 2 p w m 1 p w m 0 t i m 2 tim3 2 7 reset 22 18 c v i n 26 v hold h l f 16 17 9 8 63 2 39 29 40 41 42 1 p3 (2) 31 30 17 16 15 14 13 12 s d a 1 s d a 2 s i n s c l k s o u t 33 37 38 h s y n c v s y n c 34 r 35 g 36 b o u t 32 11 10 p2 (8) fscin s c l 1 s c l 2 s c l 3 s d a 3 28 23 filt data slicer 21 7 5 4 25 24 pwm ad1 8 pc h (8) rom program counter pc l (8) progam counter ram data bus clock generating circuit address bus rom correction circuit clock input reset input pins for data slicer i/o ports p2 6 , p2 7 sub-clock output sub-clock input osd circuit rom correction function si/o interface multi-master i 2 c-bus a-d comparator i/o port p0 i/o port p1 i/o port p2 i/o port p3 0 , p3 1 8-bit arithmetic and logical unit accumulator a (8) processor status register ps (8) stack pointer s (8) index register y (8) index register x (8) timer 6 t6 (8) timer 5 t5 (8) timer 4 t4 (8) timer 3 t3 (8) timer 2 t2 (8) timer 1 t1 (8) timer count source selection circuit control signal instruction register (8) instruction decoder output for display output port p5 2 ?5 5 synchronous signal input input port p5 0 ,p5 1
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 5 of 139 rej03b0128-0100z number of basic instructions instruction execution time clock frequency memory size input/output ports serial i/o multi-master i 2 c-bus interface a-d comparator pwm output circuit t imers rom correction function subroutine nesting interrupt clock generating circuit data slicer rom ram p0 p1 0 ?1 6 p2 0 ?2 7 p3 0 , p3 1 p5 0 , p5 1 p5 2 ?5 5 m37150m6-xxxfp m37150m8-xxxfp m37150ma-xxxfp m37150mc-xxxfp m37150mf-xxxfp m37150m6-xxxfp m37150m8-xxxfp m37150ma-xxxfp, m37150mc-xxxfp m37150mf-xxxfp, M37150EFFP 71 0.447 ms (the minimum instruction execution time, at 3.58 mhz oscillation frequency, f(x in ) = 8.95 mhz) 0.451 ms (the minimum instruction execution time, at 4.43 mhz oscillation frequency, f(x in ) = 8.86 mhz) 8.95 mhz (maximum) 24k bytes 32k bytes 40k bytes 48k bytes 60k bytes 1024 bytes (rom correction memory included) 1 152 bytes (rom correction memory included) 1472 bytes (rom correction memory included) 2048 bytes (rom correction memory included) 8-bit ? 1 (n-channel open-drain output structure, can be used as pwm output pins, int input pins, a-d input pin) 7-bit ? 1 (cmos input/output structure, however, n-channel open-drain output structure, when p1 1 ?1 4 are used as multi-master i 2 c-bus inter- face, can be used as a-d input pins, timer external clock input pins, multi- master i 2 c-bus interface) 8-bit ? 1 (p2 is cmos input/output structure, however, n-channel open- drain output structure when p2 0 and 2 1 are used as serial output, can be used as serial input/output pins, timer external clock input pins, a-d input pins, int input pin, sub-clock input/output pins) 2-bit ? 1 (cmos input/output structure, however, n-channel open-drain output structure, when used as multi-master i 2 c-bus interface, can be used as multi-master i 2 c-bus interface.) 2-bit ? 1(can be used as osd input pins) 4-bit ? 1(cmos output structures, can be used as osd output pins) 8-bit ? 1 one (three lines) 8 channels (7-bit resolution) 8-bit ? 5 8-bit ? 6 2 vectors 128 levels (maximum) <17 types> int external interrupt ? 3, internal timer interrupt ? 6, serial i/o interrupt ? 1, osd interrupt ? 1, multi-master i 2 c-bus interface interrupt ? 1, data slicer interrupt ? 1, f(x in )/4096 interrupt ? 1, v sync interrupt ? 1, brk instruction interrupt ? 1, reset ? 1 2 built-in circuits (externally connected to x cin/out is a ceramic resonator or a quartz-crystal oscillator) built-in parameter 6. performance overview t able 6.1 performance overview functions i/o i/o i/o i/o input output
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 6 of 139 rej03b0128-0100z 32 characters ? 2 lines cc mode: 16 ? 26 dots (character display area : 16 ? 20 dots) osd mode: 16 ? 20 dots 254 kinds cc mode: 1 kinds osd mode: 8 kinds 1 screen: 8 kinds (per character unit) horizontal: 128 levels, vertical: 512 levels 5v ?10% 1 65 mw typ. ( at oscillation frequency f(x in ) = 8.95 mhz, f osc = 26.85 mhz) 82.5 mw typ. ( at oscillation frequency f(x in ) = 8.95 mhz) 0.33 mw typ. ( at oscillation frequency f(x cin ) = 32 khz) 0.055 mw ( maximum ) ?0 ? to 70 ? cmos silicon gate process 42-pin plastic molded ssop power source voltage power dissipation number of display characters dot structure kinds of characters kinds of character sizes 1 screen : 8 character font coloring display position functions t able 6.2 performance overview (continued) osd function parameter in high-speed mode in low-speed mode in stop mode operating temperature range device structure package osd on osd off osd off data slicer on data slicer off data slicer off
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 7 of 139 rej03b0128-0100z pin name input/ functions output v cc , v ss power source power source: apply voltage of 5 v + 10 % (typical) to v cc , and 0 v to v ss . cnv ss cnv ss this is connected to v ss . ______ reset reset input input to enter the reset state, the reset input pin must be kept at a low for 2 ms or more (under normal v cc conditions). if more time is needed for the quartz-crystal oscillator to stabilize, this low condition should be maintained for the required time. fscin clock input input this is the input pin for the main clock generating circuit. p0 0 /pwm0 i/o port p0 i/o port p0 is an 8-bit i/o port with a direction register allowing each i/o bit to be individually p0 2 /pwm2, programmed as input or output. at reset, this port is set to input mode. the output structure p0 3 /pwm3/ad1, is n-channel open-drain output (see note.) p0 4 /pwm4/ad2, pwm output output output pins p0 0 to p0 4 are also used as pwm output pins pwm0 to pwm4, respectively. p0 5 /ad3, the output structure is n-channel open-drain output. p0 6 /int2/ad4, external interrupt input pins p0 6 and p0 7 are also used as int external interrupt input pins int2 and int1 respec p0 7 /int1 tively. analog input input pins p0 3 , p0 4 , p0 5 and p0 6 are also used as analog input pins ad1, ad2, ad3 and ad4, respectively. p1 0 /clk cont , i/o port p1 i/o i/o port p1 is a 7-bit i/o port and has basically the same functions as port p0. the output p1 1 /scl1, structure is cmos output (see note.) p1 2 /scl2, multi-master i/o pins p1 1 ?1 4 are used as scl1, scl2, sda1 and sda2 respectively, when multi-master p1 3 /sda1 , i 2 c-bus interface i 2 c-bus interface is used. the output structure is n-channel open-drain output. p1 4 /sda2, clock control output p1 0 pin is also used as clock control output clk cont. the output structure is cmos p1 5 , output. p1 6/ ad8 / tim2 external clock input p1 6 pin is also used as timer external clock input pin tim2. input for timer analog input input p1 6 pin is also used as analog input pin ad8. p2 0 /s clk /ad5, i /o por t p2 i/o port p2 is an 8-bit i/o port and has basically the same functions as port p0. the output p2 1 /s out /ad6 , structure is cmos output. (see note) p2 2 /s in /ad7, serial i/o synchronous i/o p2 0 pin is also used as serial i/o synchronous clock input/output pin s clk . the output p2 3 /tim3, clock input/output port structure is n-channel open-drain output. p2 4 /tim2, serial i/o data output p2 1 pin is also used as serial i/o data output pin s out . the output structure is open-drain p2 5 /int3 , output output. p2 6 / x cin , serial i/o data input input p2 2 pin is also used as serial i/o data input pin s in . p27/x cout external clock input pins p2 3 and p2 4 are also used as timer external clock input pins tim3 and tim2 input for timer respectively. analog input input pins p2 0 ?2 2 are also used as analog input pins ad5, ad6 and ad7 respectively. sub-clock input input p2 6 pin is also used as sub-clock input pin x cin . sub-clock output output p2 7 pin is also used as sub-clock output pin x cout . the output structure is cmos output. external interrupt input p2 5 pin is also used as int external interrupt input pin int3. input p3 0 /sda3 i/o port p3 i/o port p3 0 ,p3 1 is an 2-bit i/o port and has basically the same functions as port p0. p3 1 /scl3 the output structure is cmos output (see note.) multi-master i/o pins p3 0 ,p3 1 are used as sda3,scl3 respectively, when multi-master i 2 c-bus i 2 c-bus interface interface is used. the output structure is n-channel open-drain output. 7. pin description t able 7.1 pin description
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 8 of 139 rej03b0128-0100z notes : port pi (i = 0 to 3) has a port pi direction register that can be used to program each bit for input (?? or an output (??. the pins programmed as ??in the direction register are output pins. when pins are programmed as ?,?they are input pins. when pins are programmed as output pi ns, the output data is written into the port latch and then output. when data is read from the output pins, the data of the port latch, not the output pin level, is read. this allows a previously output value to be read correctly even if the output low voltage has risen due to, for example, a directly-driven li ght emitting diode. the input pins are in the floating state, so the values of the pins can be read. when data is written to the input pin, it is written onl y into the port latch, while the pin remains in the floating state. ? led drive ports 4 (p2 4 p2 7 ) pin name input/ functions output p5 0 /h sync input p5 input port p5 is a 2-bit input port. p5 1 /v sync horizonta synchronous signal input the p5 0 pin is also used as a horizontal synchronous signal input h sync for osd. v ertical synchronous signal input the p5 1 pin is also used as a vertical synchronous signal input v sync for osd. p5 2 /b, output p5 output pins p5 2 ?5 5 are a 4-bit output port. the output structure is cmos output. p5 3 /g, osd output output pins p5 2 ?5 5 are also used as osd output pins r, g, b and out respectively. the output p5 4 /r, structure is cmos output. p5 5 /out cv in i/o for data slicer input input the composite video signal through a capacitor. v hold input connect a capacitor between v hold and vss. hlf i/o connect a filter, consisting of a capacitor and a resistor, between hlf and vss. filt clock oscillation input connect a capacitor between filt and vss. filter t able 7.2 pin description (continued)
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 9 of 139 rej03b0128-0100z por ts p1, p2, p3 0 , p3 1 data bus por ts p0 0 ?0 7 data bus port latch direction register port latch direction register fig. 7.1 i/o pin block diagram (1) n-channel open-drain output ports p0 0 ?0 7 note : each port is also used as follows : p0 0 ?0 4 : pwm0?wm4 p0 5 : ad3 p0 6 : int2/ad4 p0 7 : int1 cmos output ports p1 , p2, p3 0 , p3 1 notes 1 : each port is also used as follows : p1 0 : clk cont p1 1 : scl1 p1 2 : scl2 p1 3 : sda1 p1 4 : sda2 p1 6 : ad8/tim2 2: the output structure of ports p1 1 ?1 4, p3 0 ?3 1 is n-channel open-drain output when using as multi-master i 2 c-bus interface (it is the same with p0 0 ?0 7 ). 3: the output structure of ports p2 0 and p2 1 is n-channel open-drain output when using as serial output (it is the same as p0 0 ?0 7 ). p2 0 : s clk /ad5 p2 1 : s out /ad6 p2 2 : s in /ad7 p2 3 : tim3 p2 4 : tim2 p2 5 : int3 p2 6 : x cin p2 7 : x cout p3 0 : sda3 p3 1 : scl3
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 10 of 139 rej03b0128-0100z cmos input ports p5 0 , p5 1 note : each pin is also used as follows : p5 0 : h sync p5 1 : v sync fig. 7.2 i/o pin block diagram (2) cmos output ports p5 2 ?5 5 note : each pin is also used as follows : p5 2 :b p5 3 :g p5 4 :r p5 5 : out internal circuit p5 2 ?5 5 p5 0 , p5 1 internal circuit
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 11 of 139 rej03b0128-0100z fscin pin the fscin pin is a reference clock input pin. the main clock and osd clock are generated based on the reference clock from the fscin pin. the sub clock can also be generated directly from the 32 khz oscillator circuit and fscin pin. x cin /x cout f(x in ) f( osc ) fscin (3.58mhz) or (4.43mhz) inside system clock of switch circuit f(x cin ) main clock clock for osd sub clock "1" "1" "1" "0" cc2 address 0211 16 bit 2 "0" cm address 00fb 16 bit 7(cm7) "0" oc2 address 00d0 16 bit 3 or 4 data slicer circuit generating circuit system clock 32khz of oscillation circuits f ( ) f(x in ) = 8.95 mhz f(osc) = 26.85 mhz at 3.58 mhz oscillation frequency f(x in ) = 8.86 mhz f(osc) = 26.58 mhz at 4.43 mhz oscillation frequency fig. 7.2 clock generating circuit
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 12 of 139 rej03b0128-0100z 8. functional description 8.1 central processing unit (cpu) this microcomputer uses the standard 740 family instruction set. refer to the table of 740 family addressing modes and machine instructions or the series 740 users manual for de- tails on the instruction set. a vailability of 740 family instructions is as follows: the fst and slw instructions cannot be used. the mul, div, wit and stp instructions can be used. 8.1.1 cpu mode register the cpu mode register includes a stack page selection bit and in- ternal system clock selection bit. the cpu mode register is allo- cated to address 00fb 16 . fig. 8.1.1 cpu mode register b7 b6 b5 b4 b3 b2 b1 b0 after reset rw cpu mode register 0, 1 2 3, 4 0 1 name functions processor mode bits (cm0, cm1) 0 0: single-chip mode 0 1: 1 0: not available 1 1: fix these bits to ?.? 1 stack page selection bit (cm2) (see note1) 1 b1 b0 0: 0 page 1: 1 page 1 0 0 5 1 6 0 main clock (x in ) stop bit (cm6) cpu mode register (cm) [address 00fb 16 ] r w rw r w r w rw x cout drivability selection bit (cm5) 0: low drive 1: high drive 0: oscillatin g 1: stopped 7 0 internal system clock selection bit (cm7) (see note2) rw 0: x in selected (high-speed mode) 1: x cin ? cout selected or fscin input selected (low-speed mode) note 1: this bit is set to ??after the reset release. 2: x cin -x cout and fscin are switched over using clock control register 2 (address 0211 16 ) bit 2. b
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 13 of 139 rej03b0128-0100z 8.2 memory 8.2.1 special function register (sfr) area the special function register (sfr) area in the zero page includes control registers such as i/o ports and timers. 8.2.2 ram ram is used for data storage and for stack area of subroutine calls and interrupts. 8.2.3 rom rom is used for storing user programs as well as the interrupt vector area. 8.2.4 osd ram ram used for specifying the character codes and colors for display. 8.2.5 osd rom rom used for storing character data for display. 8.2.6 interrupt vector area the interrupt vector area contains reset and interrupt vectors. 8.2.7 zero page the zero page addressing mode can be used to specify memory and register addresses in the zero page area. access to this area is pos- sible with only 2 bytes in the zero page addressing mode. 8.2.8 special page the special page addressing mode can be used to specify memory addresses in the special page area. access to this area is possible with only 2 bytes in the special page addressing mode. 8.2.9 rom correction memory (ram) this is used as the program area for rom correction. fig. 8.2.1 memory map (m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP) 0000 16 00c0 16 00ff 16 sfr1 area not used ffff 16 ffde 16 ff00 16 interrupt vector area special page 087f 16 0800 16 osd ram (128 bytes) zero page 0200 16 020f 16 sfr2 area not used 0300 16 00bf 16 0100 16 01ff 16 05bf 16 053f 16 not used 0b3f 16 0900 16 1000 16 not used r om correction function v ector 1: address 0300 16 v ector 2: address 0320 16 0320 16 06ff 16 6000 16 8000 16 a000 16 4000 16 m37150mf-xxxfp, M37150EFFP rom (60k bytes) m37150mc-xxxfp rom (48k bytes) m37150ma-xxxfp rom (40k bytes) m37150m8-xxxfp rom (32k bytes) 10000 16 1ffff 16 not used m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP m37150m6-xxxfp rom (24k bytes) 13bff 16 11400 16 osd rom (10k bytes) not used m37150mf-xxxfp, M37150EFFP ram (2048 bytes) m37150mb-xxxfp ram (1152 bytes) m37150ma/mc- xxxfp ram (1472 bytes) m37150m6- xxxfp ram (1024 bytes)
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 14 of 139 rej03b0128-0100z fig. 8.2.2 memory map of special function register 1 (sfr1) (1) b 7b0 b 7 b 0 d0 16 d1 16 d2 16 d3 16 d4 16 d5 16 d6 16 d7 16 d8 16 d9 16 da 16 db 16 dc 16 dd 16 de 16 df 16 c0 16 c1 16 c2 16 c3 16 c4 16 c5 16 c6 16 c7 16 c8 16 c9 16 cb 16 cc 16 cd 16 ce 16 cf 16 ca 16 port p5(p5) caption data register 3 (cd3) caption data register 4 (cd4) osd control register (oc) port p1(p1) port p1 direction register (d1) port p3(p3) port p3 direction register (d3) port p2(p2) port p2 direction register (d2) port p0(p0) port p0 direction register (d0) horizontal position register (hp) block control register 1(bc1) block control register 2(bc2) ve rtical position register 1(vp1) ve rtical position register 2(vp2) window register 1(wn1) interrupt input polarity control register (re) osd port control register (pf) window register 2(wn2) i/o polarity control register (pc) raster color register (rc) timer return set register (tms) clock control register 1 (cc1) osd control register 2(oc2) sfr1 area (addresses c0 16 to df 16 ) address register bit allocation state immediately after reset : ??immediately after reset : indeterminate immediately after reset 0 1 ? : ??immediately after reset : fix this bit to ?? (do not write ?? : function bit : no function bit : fix this bit to ?? (do not write ?? name : 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 16 00 16 00 16 00 16 00 16 00 16 00 16 ? ? ? ? 40 16 00 16 ? ? ? 00 16 00 16 ? ? 00 16 00 16 0 0 0 0 0 0 ? ? 00 16 00 16 ? 00 16 ? 0 0 1 0 0 0 0 1 ? ? 0 ? ? ? ? ? bsel21 bsel20 p31 p30 outs p31d p30d t3sc pf3 pf2 pf5 pf4 cc10 cdl27 cdl26 cdl25 cdl24 cdl23 cdl22 cdl21 cdl20 cdh27 cdh26 cdh25 cdh24 cdh23 cdh22 cdh21 cdh20 oc3 oc2 oc4 oc1 oc0 hp3 hp2 hp4 hp1 hp0 hp5 hp6 bc13 bc12 bc14 bc11 bc10 bc16 bc17 bc23 bc22 bc24 bc21 bc20 bc26 bc27 vp13 vp12 vp14 vp11 vp10 vp16 vp17 vp15 vp23 vp22 vp24 vp21 vp20 vp26 vp27 vp25 wn13 wn12 wn14 wn11 wn10 wn16 wn17 wn15 wn23 wn22 wn24 wn21 wn20 wn26 wn27 wn25 pc3 pc2 pc1 pc0 pc5 pc6 rc3 rc2 rc1 rc0 rc7 int3 int2 int1 0 1 0 0 0 0 0 tms oc7 bc15 bc25 oc21 oc20 t2sc ? ? ? 0 ? 0 0 0 0 0 0 0 0 0 ? 0 0 0 0
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 15 of 139 rej03b0128-0100z fig. 8.2.3 memory map of special function register 1 (sfr1) (2) f0 16 f1 16 f2 16 f3 16 f4 16 f5 16 f6 16 f7 16 f8 16 f9 16 fa 16 fb 16 fc 16 fd 16 fe 16 ff 16 e0 16 e1 16 e2 16 e3 16 e4 16 e5 16 e6 16 e7 16 e8 16 e9 16 eb 16 ec 16 ed 16 ee 16 ef 16 ea 16 address serial i/o register (sio) a-d control register 1 (ad1) timer 5 (t5) timer 6 (t6) timer 1 (t1) caption data register 1 (cd1) caption position register (cps) data slicer test register 2 clock run-in detect register (crd) data clock position register (dps) register data slicer control register 1 (dsc1) data slicer control register 2 (dsc2) timer 2 (t2) timer 3 (t3) timer 4 (t4) timer mode register 1 (tm1) timer mode register 2 (tm2) i 2 c data shift register (s0) i 2 c control register (s1d) i 2 c clock control register (s2) interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 1 (icon1) interrupt control register 2 (icon2) data slicer test register 1 synchronous signal counter register (hc) a-d control register 2 (ad2) cpu mode register (cpum) b7 b0 bit allocation state immediately after reset b7 b0 sfr1 area (addresses e0 16 to ff 16 ) caption data register 2 (cd2) serial i/o mode register (sm) i 2 c status register (s1) i 2 c address register (s0d) : ? immediately after reset : indeterminate immediately after reset 0 1 ? : ? immediately after reset : fix this bit to ? (do not write ?? : function bit : no function bit : fix this bit to ? (do not write ?? name : 1 0 tm20 tm21 tm22 tm23 tm24 tm10 tm11 tm12 tm13 tm14 cm2 tm1r tm2r tm3r tm4r osdr vscr in3r ck0 in1r dsr s1r tm1e tm2e tm3e tm4e osde vsce in1e dse s1e in2e tm25 00 16 ff 16 07 16 ff 16 07 16 07 16 tm15 tm16 tm17 tm26 tm27 ? sad0 sad1 sad2 sad3 sad4 sad5 sad6 rbw lrb ad0 aas al pin bb trx mst bc0 bc1 bc2 eso als bsel0 bsel1 ccr0 ccr1 ccr2 ccr3 ccr4 ack 00 16 00 16 00 16 ckr in2r iicr tm56r in3e cke iice tm56e tm56c 0 0 cm7 cm5 cm6 sm0 sm1 sm2 sm3 adc10 adc11 adc12 adc14 adc20 adc21 adc22 adc25 adc26 sm5 sm6 adc24 adc23 10bit sad f ast mode ? 00 16 00 16 00 16 ff 16 dsc10 dsc11 dsc12 dsc20 dsc23 dsc24 dsc25 crd3 crd4 crd5 crd6 crd7 dps3 dps4 dps5 dps6 dps7 cps0 cps3 cps4 cps5 cps1 cps2 cps6 cps7 hc0 hc3 hc4 hc5 hc1 hc2 0? 0? 0 ? ?? 00 0 ? 01100 01 1 0 0 00 1 0 1 00 0 0 00 16 cdh10 cdh13 cdh14 cdh15 cdh11 cdh12 cdh16 cdh17 cdl10 cdl13 cdl14 cdl15 cdl11 cdl12 cdl16 cdl17 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 d1 d2 d3 d4 d5 d6 d7 d0 0 0 00?00 0 0 0 0 01 0 0? ack bit 09 16 3c 16
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 16 of 139 rej03b0128-0100z fig. 8.2.4 memory map of special function register 2 (sfr2) sfr2 area (addresses 200 16 to 20f 16 ) b7 b0 b7 b0 200 16 201 16 202 16 203 16 204 16 206 16 205 16 207 16 208 16 209 16 20b 16 20c 16 20d 16 20e 16 20a 16 20f 16 210 16 211 16 212 16 pwm2 register (pwm2) pwm4 register (pwm4) pwm0 register (pwm0) pwm1 register (pwm1) pwm3 register (pwm3) clock frequency set register ( cfs ) pwm mode register 2 (pm2) rom correction address 1 (low-order) rom correction enable register (rcr) pwm mode register 1 (pm1) rom correction address 2 (high-order) rom correction address 1 (high-order) rom correction address 2 (low-order) clock control register 2(cc2) clock control register 3(cc3) : 0 immediately after reset : indeterminate immediately after reset 0 1 ? : 1 immediately after reset : fix this bit to 0 (do not write 1 ) : function bit : no function bit : fix this bit to 1 (do not write 0 ) name : 1 0 address register bit allocation state immediately after reset 0 0 0 00 16 00 16 00 16 00 16 00 16 0 0 0 0 1 1 1 0 ? ? ? ? 0 ? ? 0 00 16 ? pm13 pm10 rc0 cc22 cc35 00 16 pm23 pm20 pm24 pm21 pm22 rc1 0 0 0 0 1 0 0 cc37 00 16 00 16 00 16 ? ? ? ? ? ? ? 0 0 0 0 0 0 ?
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 17 of 139 rej03b0128-0100z fig. 8.2.5 internal state of processor status register and program counter at reset b 7 b0 b 7 b 0 1 r e g i s t e r processor status register (ps) b i t a l l o c a t i o ns t a t e i m m e d i a t e l y a f t e r r e s e t program counter (pc h ) program counter (pc l ) c o n t e n t s o f a d d r e s s f f f f 1 6 c ontents of address fffe 16 i z c d b t v n?? ? ? ? ? ? : fix to this bit to ?? ( do not write to 1) : < bit allocation > < s t a t e i m m e d i a t e l y a f t e r r e s e t > f u n c t i o n b i t : n o f u n c t i o n b i t : fix to this bit to ?? ( do not write to 0) n a m e : : 0 i m m e d i a t e l y a f t e r r e s e t : i ndeterminate immediately after reset 0 1 ? : 1 i m m e d i a t e l y a f t e r r e s e t 1 0
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 18 of 139 rej03b0128-0100z priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 8.3 interrupts interrupts can be caused by 17 different sources comprising 4 exter- nal, 11 internal, 1 software, and 1 reset interrupts. interrupts are vec- tored interrupts with priorities as shown in table 8.3.1. reset is also included in the table as its operation is similar to an interrupt. when an interrupt is accepted, ? the contents of the program counter and processor status regis ter are automatically stored into the stack. ? the interrupt disable flag i is set to ??and the corresponding interrupt request bit is set to ?. ? the jump destination address stored in the vector address enters the program counter. other interrupts are disabled when the in terrupt disable flag is set to ?. all interrupts except the brk instruction interrupt have an inter rupt request bit and an interrupt enable bit. the interrupt request bits are in interrupt request registers 1 and 2 and the interrupt enable bits are in interrupt control registers 1 and 2. figures 8.3.2 to 8.3.6 show the interrupt-related registers. interrupts other than the brk instruction interrupt and reset are accepted when the interrupt enable bit is ?,?interrupt request bit is ?,?and the interrupt disable flag is ?.?the interrupt request bit can be set to ??by a program, but not set to ?.?the interrupt enable bit can be set to ??and ??by a program. reset is treated as a non-maskable interrupt with the highest pri ority. figure 8.3.1 shows interrupt controls. 8.3.1 interrupt causes (1)v sync , osd interrupts the v sync interrupt is an interrupt request synchronized with the vertical sync signal. the osd interrupt occurs after charac- ter block display to the crt is completed. (2)int1 to int3 external interrupts the int1 to int3 interrupts are external interrupt inputs; the sys- tem detects that the level of a pin changes from low to high or from high to low, and generates an interrupt request. the in- put active edge can be selected by bits 0 to 2 of the interrupt input polarity register (address 00dc 16 ); when this bit is ?,?a change from low to high is detected; when it is ?,?a change from high to low is detected. note that both bits are cleared to ??at reset. (3)timers 1 to 4 interrupts an interrupt is generated by an overflow of timers 1 to 4. (4)serial i/o interrupt this is an interrupt request from the clock synchronous serial i/o function. v ector addresses ffff 16 , fffe 16 fffd 16 , fffc 16 fffb 16 , fffa 16 fff9 16 , fff8 16 fff7 16 , fff6 16 fff5 16 , fff4 16 fff3 16 , fff2 16 fff1 16 , fff0 16 ffef 16 , ffee 16 ffed 16 , ffec 16 ffeb 16 , ffea 16 ffe9 16 , ffe8 16 ffe7 16 , ffe6 16 ffe5 16 , ffe4 16 ffe3 16 , ffe2 16 ffdf 16 , ffde 16 interrupt source reset osd interrupt int1 external interrupt data slicer interrupt serial i/o interrupt t imer 4 interrupt f(x in )/4096 interrupt v sync interrupt t imer 3 interrupt t imer 2 interrupt t imer 1 interrupt int3 external interrupt int2 external interrupt multi-master i 2 c-bus interface interrupt t imer 5 ?6 interrupt brk instruction interrupt remarks non-maskable active edge selectable active edge selectable active edge selectable source switch by software (see note) non-maskable ta ble 8.3.1 interrupt vector addresses and priority note: switching a source during a program causes an unnecessary interrupt. therefore, set a source at initializing of program.
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 19 of 139 rej03b0128-0100z (5) f(x in )/4096 interrupt the f(x in )/4096 interrupt occurs regularly with a period of f(x in )/ 4096. set bit 0 of the pwm mode register 1 to ?. (6) data slicer interrupt an interrupt occurs when slicing data is completed. (7) multi-master i 2 c-bus interface interrupt this is an interrupt request related to the multi-master i 2 c-bus interface. (8) timer 5 ?6 interrupt an interrupt is generated by an overflow of timer 5 or 6. their priorities are same, and can be switched by software. (9) brk instruction interrupt this software interrupt has the least significant priority. it does not have a corresponding interrupt enable bit, and it is not af- fected by the interrupt disable flag i (non-maskable). fig. 8.3.1 interrupt control in terrupt request bi t interrupt enable bi t interrupt disable flag i brk inst ruct ion r e s e t i n t e r r u p t r e q u e s t
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 20 of 139 rej03b0128-0100z fig. 8.3.2 interrupt request register 1 fig. 8.3.3 interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 interrupt request register 1 (ireq1) [address 00fc 16 ] w r interrupt request register 1 0 b name functions afrer reset 0 : no interrupt request issued 1 : interrupt request issued timer 1 interrupt request bit (tm1r) 1 timer 2 interrupt request bit (tm2r) 2 timer 3 interrupt request bit (tm3r) 3t imer 4 interrupt request bit (tm4r) 4 osd interrupt request bit (osdr) 5 vsync interrupt request bit (vscr) 6 int3 external interrupt request bit (in3r) 7 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 0 0 0 0 0 0 0 ? : ??can be set by software, but ??cannot be set. ? r ? r ? r ? r ? r ? r ? r r nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is ?. b7 b6 b5 b4 b3 b2 b1 b0 interrupt request register 2 (ireq2) [address 00fd 16 ] after reset rw interrupt request register 2 0 b int1 external interrupt name functions request bit (in1r) 0 : no interrupt request issued 1 : interrupt request issued 1 data slicer interrupt request bit (dsr ) 2 serial i/o interrupt request bit (sir) 3 4 int2 external interrupt request bit (in2r) 5 7f ix this bit to ?. 0 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 ? : ??can be set by software, but ??cannot be set. 0 0 ? 0 0 ? 0 ? 0 ? 0 : no interrupt request issued 1 : interrupt request issued r r r r ? r r ? rw f(x in )/4096 interrupt request bit (ckr) 0 : no interrupt request issued 1 : interrupt request issued multi-master i 2 c-bus interrupt request bit (iicr) 0 : no interrupt request issued 1 : interrupt request issued 6t imer 5 ?6 interrupt request bit (tm56r) 0 : no interrupt request issued 1 : interrupt request issued 0 ? r
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 21 of 139 rej03b0128-0100z fig. 8.3.4 interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 interrupt control register 1 (icon1) [address 00fe 16 ] b name after reset function s rw interrupt control register 1 0 timer 1 interrupt enable bit (tm1e) 0 : interrupt disabled 1 : interrupt enabled 1 timer 2 interrupt enable bit (tm2e) 2 timer 3 interrupt enable bit (tm3e ) 3 4 osd interrupt enable bit (osde) 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 0 0 0 0 0 rw rw rw rw rw r 7 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is ?. timer 4 interrupt enable bit (tm4e) 0 : interrupt disabled 1 : interrupt enabled 5 v sync interrupt enable bit (vsce) 0 : interrupt disabled 1 : interrupt enabled 0 rw 6 int3 external interrupt enable bit (in3e) 0 : interrupt disabled 1 : interrupt enabled 0 rw fig. 8.3.5 interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 interrupt control register 2 (icon2) [address 00ff 16 ] b name function s after reset rw interrupt control register 2 0 int1 external interrupt enable bit (in1e) 0 : interrupt disabled 1 : interrupt enabled 1 data slicer interrupt enable bit (dse) 2 serial i/o interrupt enable bit (sie) 3 4 int2 external interrupt enable bit (in2e) 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 0 0 0rw rw rw rw 0rw f(x in )/4096 interrupt enable bit (cke) 0 : interrupt disabled 1 : interrupt enabled 5 multi-master i 2 c-bus interface interrupt enable bit (iice) 0 : interrupt disabled 1 : interrupt enabled 6 timer 5 ?6 interrupt enable bit (tm56e ) 0 : interrupt disabled 1 : interrupt enabled 7 timer 5 ?6 interrupt switch bit (tm56c) 0 : timer 5 1 : timer 6 0rw 0rw 0rw
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 22 of 139 rej03b0128-0100z fig. 8.3.6 interrupt input polarity register b7 b6 b5 b4 b3 b2 b1 b0 interrupt input polarity register (re) [address 00dc 16 ] b name functions after reset r w interrupt input polarity register int1 polarity switch bit (int1) 0 0 0 0 : positive polarity 1 : negative polarity 0 1 0 : positive polarity 1 : negative polarity 2 3 to 7 int2 polarity switch bit (int2) int3 polarity switch bit (int3) nothing is assigned. these bits are write disable bits. when these bits are read out, the values are ?. 0rw rw rw r 0 : positive polarity 1 : negative polarity
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 23 of 139 rej03b0128-0100z 8.4 timers this microcomputer has 6 timers: timer 1, timer 2, timer 3, timer 4, timer 5, and timer 6. all timers are 8-bit timers with the 8-bit timer latch. the timer block diagram is shown in figure 8.4.3. all of the timers count down and their divide ratio is 1/(n+1), where n is the value of timer latch. by writing a count value to the correspond- ing timer latch (addresses 00f0 16 to 00f3 16 : timers 1 to 4, addresses 00ee 16 and 00ef 16 : timers 5 and 6), the value is also set to a timer, simultaneously. the count value is decremented by 1. the timer interrupt request bit is set to ??by a timer overflow at the next count pulse, after the count value reaches ?0 16 ? 8.4.1 timer 1 t imer 1 can select one of the following count sources: f(x in )/16 or f(x cin )/16 f(x in )/4096 or f(x cin )/4096 external clock from the tim2 pin the count source of timer 1 is selected by setting bits 5 and 0 of timer mode register 1 (address 00f4 16 ). either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. t imer 1 interrupt request occurs at timer 1 overflow. 8.4.2 timer 2 t imer 2 can select one of the following count sources: f(x in )/16 or f(x cin )/16 t imer 1 overflow signal external clock from the tim2 pin the count source of timer 2 is selected by setting bits 4 and 1 of timer mode register 1 (address 00f4 16 ). either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. when timer 1 overflow signal is a count source for the timer 2, the timer 1 functions as an 8- bit prescaler. t imer 2 interrupt request occurs at timer 2 overflow. 8.4.3 timer 3 t imer 3 can select one of the following count sources: f(x in )/16 or f(x cin )/16 f(x cin ) external clock from the tim3 pin the count source of timer 3 is selected by setting bit 0 of timer mode register 2 (address 00f5 16 ) and bit 6 at address 00c7 16 . either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. t imer 3 interrupt request occurs at timer 3 overflow. 8.4.4 timer 4 t imer 4 can select one of the following count sources: f(x in )/16 or f(x cin )/16 f(x in )/2 or f(x cin )/2 f(x cin ) the count source of timer 3 is selected by setting bits 1 and 4 of the timer mode register 2 (address 00f5 16 ). either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. when timer 3 overflow signal is a count source for the timer 4, the timer 3 functions as an 8- bit prescaler. t imer 4 interrupt request occurs at timer 4 overflow. 8.4.5 timer 5 t imer 5 can select one of the following count sources: f(x in )/16 or f(x cin )/16 t imer 2 overflow signal t imer 4 overflow signal the count source of timer 3 is selected by setting bit 6 of timer mode register 1 (address 00f4 16 ) and bit 7 of the timer mode register 2 (address 00f5 16 ). when overflow of timer 2 or 4 is a count source for timer 5, either timer 2 or 4 functions as an 8-bit prescaler. either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. t imer 5 interrupt request occurs at timer 5 overflow. 8.4.6 timer 6 t imer 6 can select one of the following count sources: f(x in )/16 or f(x cin )/16 t imer 5 overflow signal the count source of timer 6 is selected by setting bit 7 of the timer mode register 1 (address 00f4 16 ). either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. when timer 5 overflow signal is a count source for timer 6, the timer 5 functions as an 8-bit prescaler. t imer 6 interrupt request occurs at timer 6 overflow. at reset, timers 3 and 4 are connected by hardware and ?f 16 ?is automatically set in timer 3; ?7 16 ?in timer 4. the f(x in ) ? /16 is se- lected as the timer 3 count source. the internal reset is released by timer 4 overflow in this state and the internal clock is connected. at execution of the stp instruction, timers 3 and 4 are connected by hardware and ?f 16 ?is automatically set in timer 3; ?7 16 ?in timer 4. however, the f(x in ) ? /16 is not selected as the timer 3 count source. so set both bit 0 of timer mode register 2 (address 00f5 16 ) and bit 6 at address 00c7 16 to ??before the execution of the stp instruction (f(x in ) ? /16 is selected as timer 3 count source). the internal stp state is released by timer 4 overflow in this state and the internal clock is connected. as a result of the above procedure, the program can start under a stable clock. ? : when cpu mode register bit 7 (cm7) = 1, f(x in ) becomes f(x cin ). the timer-related registers is shown in figures 8.4.1 and 8.4.2. the input path for the tim2 pin can be selected between ports p1 6 or p2 4 . use port p3 direction register (address 00c7 16 ) bit 7 to select either port.
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 24 of 139 rej03b0128-0100z fig. 8.4.2 timer mode register 2 b6 b5 b4 b3 b2 b1 b0 timer mode register 2 (tm2) [address 00f5 16 ] b after reset rw 0 name functions timer 3 count source selection bit (tm20) 0 rw 1, 4 timer 4 count source selection bits (tm21, tm24) 0r w 2 3 0 timer 3 count stop bit (tm22) 0: count start 1: count stop timer 4 count stop bit (tm23) 0: count start 1: count stop 0 0 5 timer 5 count stop bit (tm25) 0: count start 1: count stop 0 6 timer 6 count stop bit (tm26) 0: count start 1: count stop 0 rw rw rw rw rw 7 timer 5 count source selection bit 1 (tm27) 0: f(x in )/16 or f(x cin )/16 (see note) 1: count source selected by bit 6 of tm1 b0 00 : f(x in )/16 or f(x cin )/16 (see note) 10 : f(x cin ) 01 : 11 : (b6 at address 00c7 16 ) external clock from tim3 pin b4 b1 00 : timer 3 overflow signal 01 : f(x in )/16 or f(x cin )/16 (see note) 10 : f(x in )/2 or f(x cin )/2 (see note) 11 : f(x cin ) note: either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. b7 timer mode register 2 fig. 8.4.1 timer mode register 1 b7 b6 b5 b4 b3 b2 b1 b0 timer mode register 1 (tm1) [address 00f4 16 ] b after reset w timer mode register 1 0 1 2 3 4 name functions timer 1 count source selection bit 1 (tm10) 0: f(x in )/16 or f(x cin )/16 (see note) 1: count source selected by bit 5 of tm 1 timer 2 count source selection bit 1 (tm11) 0: count source selected by bit 4 of tm1 1: external clock from tim2 pin timer 1 count stop bit (tm12) 0: count start 1: count stop timer 2 count stop bit (tm13) 0: count start 1: count stop timer 2 count source selection bit 2 (tm14) r 0 0 0 0 0 w r w r w r w r w r 0: f(x in )/16 or f(x cin )/16 (see note) 1: timer 1 overflow 5 timer 1 count source selection bit 2 (tm15) 0: f(x in )/4096 or f(x cin )/4096 (see note) 1: external clock from tim2 pin 0w r 6 timer 5 count source selection bit 2 (tm16) 0: timer 2 overflow 1: timer 4 overflow 0w r 7 timer 6 internal count source selection bit (tm17) 0w r 0: f(x in )/16 or f(x cin )/16 (see note) 1: timer 5 overflow note: either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register.
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 25 of 139 rej03b0128-0100z fig. 8.4.4 timer return setting register timer return setting register timer return setting register (tms) [address 00cc 16 ] b7 b6 b5 b4 b3 b2 b1 b0 0w r fix these bits to "0." fix this bit to "1." fix this bit to "0." 7 0 stop mode return selection bit (tms) 0: timer count "07ff 16 " 1: timer count variable w r 6 0 w r 5 0 w r 0 1 0 0 0 0 0 name b functions after reset r w 0 to 4 fig. 8.4.3 port p3 direction register 0 1 2 po rt p3 direction register (see note 1) 0 w r b7 b6 b5 b4 b3 b2 b1 b 0 0 w r 0 w r 0 w r 3 output amplitude level selection bit (outs) (see note 2) 0 : 2 value output 1 : 3 value output fix this bit to "0." 4 , 5 nothing is assigned fix these bits when this bit are read out, the value are "0." 0 r 6 7 timer 3 (t3sc) refer to explanation of a timer 0 : p2 4 input 1 : p1 6 input timer 2 0 w r 0 w r 0 notes 1 : when using the port as the i 2 c-bus interface, set the port p3 direction register to 1. 2 : use the clock control register 3 (address 0212 16 ) bit 5 to select the binary output level of out. (t2sc) po rt p3 direction register po rt p3 direction register (d3) [address 00c7 16 ] b name functions after reset r w 0 : port p3 0 input 1 : port p3 0 output 0 : port p3 1 input 1 : port p3 1 output
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 26 of 139 rej03b0128-0100z fig. 8.4.5 timer block diagram timer 1 (8 ) 1/4096 1/2 cm7 tm15 1/ 8 timer 1 latch (8 ) 8 8 8 tm10 tm12 tm14 tm11 tm13 timer 2 (8) timer 2 latch (8 ) 8 8 8 timer 3 (8) timer 3 latch (8 ) 8 8 8 timer 4 (8) timer 4 latch (8) 8 8 8 timer 5 (8) timer 5 latch (8 ) 8 8 8 timer 6 (8) timer 6 latch (8 ) 8 8 8 data bus timer 1 interrupt request timer 2 interrupt request timer 3 interrupt request reset stp instruction tm20 tm22 t3sc timer 4 interrupt request tm24 tm23 tm21 tm16 timer 5 interrupt request tm27 tm25 timer 6 interrupt request tm17 tm26 tm21 tim2 tim3 selection gate: connected to black side at reset tm1 : timer mode register 1 tm2 : timer mode register 2 t3sc : timer 3 count source switch bit (address 00c7 16 ) cm : cpu mode register notes 1: high pulse width of external clock inputs tim2 and tim3 needs 4 machine cycles or more. 2: when the external clock source is selected, timers 1, 2, and 3 are counted at a rising edge of input signal . ff 16 07 16 3: in the stop mode or the wait mode, external clock inputs tim2 and tim3 cannot be used. x cin f(x in ) cc2 fscin mcu reference clock set up by the clock frequency setting register
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 27 of 139 rej03b0128-0100z 8 serial i/o shift register (8) data bus serial i/o interrupt request selection gate: connect to black side at reset. synchronous circuit frequency divider 1/8 1/4 1/16 sm1 sm0 serial i/o counter (8) sm5 : lsb msb s sm2 1/2 f(x in ) s in s out s clk 1/2 x cin 1/2 cm7 1/2 note : when the data is set in the serial i/o register (address 00ea (see note) cm : cpu mode register sm : serial i/o mode register 16 ), the register functions as the serial i/o shift register. p2 0 latch sm3 p2 1 latch sm3 sm6 8.5 serial i/o this microcomputer has a built-in serial i/o which can either transmit or receive 8-bit data serially in the clock synchronous mode. the serial i/o block diagram is shown in figure 8.5.1. the synchro- nous clock i/o pin (s clk ), and data output pin (s out ) also function as port p4, data input pin (s in ) also functions as port p2 0 ?2 2 . bit 3 of the serial i/o mode register (address 00eb 16 ) selects whether the synchronous clock is supplied internally or externally (from the s clk pin). when an internal clock is selected, bits 1 and 0 select whether f(x in ) or f(x cin ) is divided by 8, 16, 32, or 64. to use the s in pin for serial i/o, set the corresponding bit of the port p2 direction register (address 00c5 16 ) to ?. fig. 8.5.1 serial i/o block diagram the operation of the serial i/o is described below. the operation of the serial i/o differs depending on the clock source; external clock or internal clock.
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 28 of 139 rej03b0128-0100z internal clock : the serial i/o counter is set to ??during the write cycle into the serial i/o register (address 00ea 16 ), and the transfer clock goes high forcibly. at each falling edge of the transfer clock after the write cycle, serial data is output from the s out pin. transfer direction can be selected by bit 5 of the serial i/o mode register. at each rising edge of the transfer clock, data is input from the s in pin and data in the serial i/o register is shifted 1 bit. after the transfer clock has counted 8 times, the serial i/o counter becomes ??and the transfer clock stops at high. at this time the interrupt request bit is set to ?. fig. 8.5.2 serial i/o timing (for lsb first) sy nchronous cloc k tr ansfer clock serial i/o register write sig nal s e r i a l i / o o u t p u t s o u t d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 (note) s e r i a l i / o i n p u t s i n n o t e : w h e n a n i n t e r n a l c l o c k i s s e l e c t e d , t h e s o u t p i n i s a t h i g h - i m p e d a n c e a f t e r t r a n s f e r i s c o m p l e t e d . interrupt request bit is set to 1 external clock : the an external clock is selected as the clock source, the interrupt request is set to ??after the transfer clock has been counted 8 counts. however, transfer operation does not stop, so the clock should be controlled externally. use the external clock of 1 mhz or less with a duty cycle of 50%. the serial i/o timing is shown in figure 8.5.2. when using an exter- nal clock for transfer, the external clock must be held at high for initializing the serial i/o counter. when switching between an inter- nal clock and an external clock, do not switch during transfer. also, be sure to initialize the serial i/o counter after switching. notes 1: on programming, note that the serial i/o counter is set by writing to the serial i/o register with the bit managing instructions, such as seb and clb. 2: when an external clock is used as the synchronous clock, write trans- mit data to the serial i/o register when the transfer clock input level is high.
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 29 of 139 rej03b0128-0100z fig. 8.5.3 serial i/o mode register b7 b6 b5 b4 b3 b2 b1 b0 serial i/o mode register (sm) [address 00eb 16 ] b name functions after reset rw serial i/o mode register 0, 1 internal synchronous clock selection bits (sm0, sm1) b1 b0 0 0: f(x in )/8 or f(x cin )/8 0 1: f(x in )/16 or f(x cin )/16 1 0: f(x in )/32 or f(x cin )/32 1 1: f(x in )/64 or f(x cin )/64 2 synchronous clock selection bit (sm2) 3 port function selection bit (sm3) 4 5 tr ansfer direction selection bit (sm5) 0 0: p2 0 , p2 1 1: s clk , s out 0: external clock 1: internal clock 0: lsb first 1: msb first 6 fix this bit to ?. 0 0 0 0 0 0 transf er clock input pin selection bit (sm6) 0: input signal from s in pin 1: input signal from s out pin rw rw rw r w rw rw 0 7 fix this bit to ?. 0r w
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 30 of 139 rej03b0128-0100z function in conformity with philips i 2 c-bus standard: 10-bit addressing format 7-bit addressing format high-speed clock mode standard clock mode in conformity with philips i 2 c-bus standard: master transmission master reception slave transmission slave reception 16.1 khz to 400 khz ( = at 4 mhz) t able 8.6.1 multi-master i 2 c-bus interface functions item format communication mode scl clock frequency : system clock = f(x in )/2 note : we are not responsible for any third partys infringement of patent rights or other rights attributable to the use of the control function (bits 6 and 7 of the i 2 c control register at address 00f9 16 ) for connections between the i 2 c-bus interface and ports (scl1, scl2, sda1, sda2). = 8.95/2 mhz at fscin = 3.58 mhz = 8.86/2 mhz at fscin = 4.43 mhz 8.6 multi-master i 2 c-bus interface the multi-master i 2 c-bus interface is a serial communications cir- cuit, conforming to the philips i 2 c-bus data transfer format. this interface, offering both arbitration lost detection and synchronous function, is useful for multi-master serial communications. figure 8.6.1 shows a block diagram of the multi-master i 2 c-bus in- terface and table 8.6.1 shows multi-master i 2 c-bus interface func- tions. this multi-master i 2 c-bus interface consists of the address register, the data shift register, the clock control register, the control register, the status register and other control circuits. fig. 8.6.1 block diagram of multi-master i 2 c-bus interface i 2 c address register (s0d) b7 b0 sad6 sad5 sad4 sad3 sad2 sad1 sad0 rbw noise elimination circuit serial data (sda) address comparator b7 i 2 c data shift register b0 data control circuit i 2 c clock control register (s2) system clock ( ) interrupt generating circuit interrupt request signal (iicirq) b7 mst trx bb p in al aas ad0 lr b b0 i 2 c status register (s1) b7 b0 bsel1 bsel0 10bit sad als bc2 bc1 bc0 i 2 c control register (s1d) i 2 c control register (s1d) bit counter bb circui t clock control circui t noise elimination circuit serial clock (scl) b7 b0 ack ack bit fast mode ccr4 ccr3 ccr2 ccr1 ccr0 internal data bus clock division s0 al circui t eso
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 31 of 139 rej03b0128-0100z 8.6.1 i 2 c data shift register the i 2 c data shift register (s0 : address 00f6 16 ) is an 8-bit shift register to store receive data and write transmit data. when transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the scl clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. when data is received, it is input to this register from bit 0 in synchronization with the scl clock, and each time one-bit data is input, the data of this register are shifted one bit to the left. the i 2 c data shift register is in a write enable status only when the eso bit of the i 2 c control register (address 00f9 16 ) is ?.?the bit counter is reset by a write instruction to the i 2 c data shift register. when both the eso bit and the mst bit of the i 2 c status register (address 00f8 16 ) are ?,?the scl is output by a write instruction to the i 2 c data shift register. reading data from the i 2 c data shift regis- ter is always enabled regardless of the eso bit value. note: to write data into the i 2 c data shift register after setting the mst bit to ??(slave mode), keep an interval of 8 machine cycles or more. fig. 8.6.2 i 2 c data shift register b7 b6 b5 b4 b3 b2 b1 b0 i 2 c data shift register 1(s0) [address 00f6 16 ] after reset functions name b w r w r i 2 c data shift register 0 to 7 this is an 8-bit shift register to store receive data and write transmit data. indeterminate note : to write data into the i 2 c data shift register after setting the mst bit to ?0? (slave mode), keep an interval of 8 machine cycles or more. d0 to d7
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 32 of 139 rej03b0128-0100z 8.6.2 i 2 c address register the i 2 c address register (address 00f7 16 ) consists of a 7-bit slave address and a read/write bit. in the addressing mode, the slave ad- dress written in this register is compared with the address data to be received immediately after the start condition is detected. (1) bit 0: read/write bit (rbw) not used when comparing addresses in the 7-bit addressing mode. in the 10-bit addressing mode, the first address data to be received is compared with the contents (sad6 to sad0 + rbw) of the i 2 c address register. the rbw bit is cleared to ??automatically when the stop condition is detected. (2) bits 1 to 7: slave address (sad0?ad6) these bits store slave addresses. regardless of the 7-bit address- ing mode and the 10-bit addressing mode, the address data trans- mitted from the master is compared with the contents of these bits. fig. 8.6.3 i 2 c address register b7 b6 b5 b4 b3 b2 b1 b0 0 b name functions after reset rw read/write bit (rbw) 1 to 7 slave address (sad0 to sad6) the last significant bit of address data is compared. 0: wait the first byte of slave address after start condition (read state) 1: wait the first byte of slave address after restart condition (write state) the address data is compared. i 2 c address register i 2 c address register (s0d) [address 00f7 16 ] 0 0 r? rw
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 33 of 139 rej03b0128-0100z 8.6.3 i 2 c clock control register the i 2 c clock control register (address 00fa 16 ) is used to set ack control, scl mode and scl frequency. (1) bits 0 to 4: scl frequency control bits (ccr0?cr4) these bits control the scl frequency. (2) bit 5: scl mode specification bit (fast mode) this bit specifies the scl mode. when this bit is set to ?,?the stan- dard clock mode is set. when the bit is set to ?,? the high-speed clock mode is set. (3) bit 6: ack bit (ack bit) this bit sets the sda status when an ack clock ? is generated. when this bit is set to ?,?the ack return mode is set and sda goes to low at the occurrence of an ack clock. when the bit is set to ?, the ack non-return mode is set. the sda is held in the high status at the occurrence of an ack clock. however, when the slave address matches the address data in the reception of address data at ack bit = ?,? the sda automatically goes to low (ack is returned). if there is a mismatch between the slave address and the address data, the sda automatically goes to high (ack is not returned). ? ack clock: clock for acknowledgement fig. 8.6.4 i 2 c clock control register (4) bit 7: ack clock bit (ack) this bit specifies a mode of acknowledgment which is an acknowl- edgment response of data transmission. when this bit is set to ?, the no ack clock mode is set. in this case, no ack clock occurs after data transmission. when the bit is set to ?,?the ack clock mode is set and the master generates an ack clock upon comple- tion of each 1-byte data transmission.the device for transmitting address data and control data releases the sda at the occurrence of an ack clock (make sda high) and receives the ack bit generated by the data receiving device. note: do not write data into the i 2 c clock control register during transmission. if data is written during transmission, the i 2 c clock generator is reset, so that data cannot be transmitted normally. b7 b6 b5 b4 b3 b2 b1 b0 i 2 c clock control register (s2) [address 00fa 16 ] i 2 c clock control register 0 to 4 scl frequency control bits (ccr0 to ccr4) 7 5 6 scl mode specification bit (fast mode) 0: standard clock mode 1: high-speed clock mode 0 standard clock mode functions name after reset rw b 0 0 0 ack bit (ack bit) ack clock bit (ack) 0: ack is returned. 1: ack is not returned. 0: no ack clock 1: ack clock high speed clock mode setup disabled setup disabled 00 to 02 setup disabled 333 03 setup disabled 250 04 100 400 (see note) 05 83.3 166 06 500/ccr value 1000/ccr value ... 17.2 34.5 1d 16.6 33.3 1e 16.1 32.3 1f ( notes 1. at 400khz in the high-speed clock mode, the duty is as below . ?0? period : ?1? period = 3 : 2 in the other cases, the duty is as below. ?0? period : ?1? period = 1 : 1 2. at fscin = 3.58 mhz, = 8.95/2 mhz at fscin = 4.43 mhz, = 8.86/2 mhz values shown in table is as below : at fscin = 3.58 mhz, each value ? ?
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 34 of 139 rej03b0128-0100z 8.6.4 i 2 c control register the i 2 c control register (address 00f9 16 ) controls the data commu- nication format. (1) bits 0 to 2: bit counter (bc0?c2) these bits decide the number of bits for the next 1-byte data to be transmitted. an interrupt request signal occurs immediately after the number of bits specified with these bits are transmitted. when a start condition is received, these bits become ?00 2 ?and the address data is always transmitted and received in 8 bits. (2) bit 3: i 2 c interface use enable bit (eso) this bit enables usage of the multimaster i 2 c bus interface. when this bit is set to ?,?interface is in the disabled status, so the sda and the scl become high-impedance. when the bit is set to ?,?use of the interface is enabled. when eso = ?,?the following is performed. pin = ?,?bb = ??and al = ??are set (bits of the i 2 c status register at address 00f8 16 ). ? riting data to the i 2 c data shift register (address 00f6 16 ) is dis- abled. (3) bit 4: data format selection bit (als) this bit decides whether or not to recognize slave addresses. when this bit is set to ?,?the addressing format is selected, so that ad- dress data is recognized. when a match is found between a slave address and address data as a result of comparison or when a gen- eral call (refer to ?.6.5 i 2 c status register,?bit 1) is received, trans- mission processing can be performed. when this bit is set to ?,?the free data format is selected, so that slave addresses are not recog- nized. (4) bit 5: addressing format selection bit (10bit sad) this bit selects a slave address specification format. when this bit is set to ?,?the 7-bit addressing format is selected. in this case, only the high-order 7 bits (slave address) of the i 2 c address register (ad- dress 00f7 16 ) are compared with address data. when this bit is set to ?,?the 10-bit addressing format is selected and all the bits of the i 2 c address register are compared with the address data. (5) bits 6 and 7: connection control bits between i 2 c-bus interface and ports (bsel0, bsel1) these bits control the connection between scl and ports or sda and ports (refer to figure 8.6.5). note: to connect with scl3 and sda3, set bits 2 and 3 of the port p3 register (00c6 16 ) . fig. 8.6.5 connection port control by bsel0 and bsel1 bsel0 bsel1 bsel0 scl1/p1 1 scl2/p1 2 sda1/p1 3 sda2/p1 4 bsel1 scl sda ?1? ?0? ?1? scl3/p3 1 sda3/p3 0 bsel20 bsel20 ?0? ?1? ?0? ?1? ?0? ?1? ?0? ?1? ?0? ?1? ?0? ?1? bsel21 bsel21 ?0? multi-master i 2 c-bus interface notes the paths scl1, scl2, sda1, and sda2, as well as the paths scl3 and sda3 cannot be connected at the same time. port p3 register (address 00c6 16 ) bit 3 is used to control the pin connections of scl3/p3 1 and scl1/p1 1 and those of sda3/p3 0 and sda1/p1 3 . set the corresponding direction register to "1" to use the port as multi-master i 2 c-bus interface.
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 35 of 139 rej03b0128-0100z fig. 8.6.6 i 2 c control register b7 b6 b5 b4 b3 b2 b1 b0 0 to 2 bit counter (number of transmit/recieve bits) (bc0 to bc2 ) b2 b1 b0 0 0 0 : 8 0 0 1 : 7 0 1 0 : 6 0 1 1 : 5 1 0 0 : 4 1 0 1 : 3 1 1 0 : 2 1 1 1 : 1 3i 2 c-bus interface use enable bit (eso) 0: disabled 1: enabled 4d ata format selection bit(als) 0: addre ssing mode 1: free data format 5a ddressing format selection bit (10bit sad) 0: 7- bit addressing format 1: 10-bit addressing format 6, 7 connection control bits between i 2 c-bus interface and ports (bsel0, bsel1) b7 b6 connection port (see note) 0 0: none 0 1: scl1, sda1 1 0: scl2, sda2 1 1: scl1, sda1 0 0 0 0 0 i 2 c control register (s1d) [address 00f9 16 ] i 2 c control register b name function s after reset r w note: set the corresponding direction register to "1" to use the port as multi-master i 2 c-bus interface. to use scl1, sda1, scl2 and sda2, set the port p3 register (address 00c6 16 ) bit 2 to 0. r w r w r w r w r w scl2, sda2 fig. 8.6.7 port p3 register port p3 register (p3) [address 00c6 16 ] port p3 register 0 1 2 port p3 register indeterminate indeterminate w r 4 to 7 b7 b6 b5 b4 b3 b2 b1 b0 nothing is assigned. this bit is write disable bit. when this bit is read out, the value is "0." w r 0 w r 0 ? r 3 (bsel20 ) (see note) 0 w r scl3/p3 1 -scl1/p1 1 sda3/p3 0 -sda1/p1 3 connection control bit (bsel21) notes for the ports used as the multi-master i 2 c-bus interface, set their direction registers to 1. to use scl3 and sda3, set the i 2 c control register (address 00f9 16 ) bits 6?7 to 0. bn ame functions after reset r w port p3 0 data port p3 1 data switch bit of i 2 c-bus interface and port p3 0 : port p3 0 , port p3 1 1 : i 2 cbus (sda3,scl3) 0 : cutting 1 : connection
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 36 of 139 rej03b0128-0100z 8.6.5 i 2 c status register the i 2 c status register (address 00f8 16 ) controls the i 2 c-bus inter- face status. the low-order 4 bits are read-only bits and the high- order 4 bits can be read out and written to. (1) bit 0: last receive bit (lrb) this bit stores the last bit value of received data and can also be used for ack receive confirmation. if ack is returned when an ack clock occurs, the lrb bit is set to ?.?if ack is not returned, this bit is set to ?.? except in the ack mode, the last bit value of received data is input. the state of this bit is changed from ??to ??by executing a write instruction to the i 2 c data shift register (address 00f6 16 ). (2) bit 1: general call detecting flag (ad0) this bit is set to ??when a general call ? whose address data is all ??is received in the slave mode. by a general call of the master device, every slave device receives control data after the general call. the ad0 bit is set to ??by detecting the stop condition or start condition. ? general call: the master transmits the general call address ?0 16 to all slaves. (3) bit 2: slave address comparison flag (aas) this flag indicates a comparison result of address data. in the slave receive mode, when the 7-bit addressing format is selected, this bit is set to ??in either of the following conditions. the address data immediately after occurrence of a start con- dition matches the slave address stored in the high-order 7 bits of the i 2 c address register (address 00f7 16 ). ? general call is received. in the slave reception mode, when the 10-bit addressing format is selected, this bit is set to ??in the following condition. when the address data is compared with the i 2 c address regis- ter (8 bits consisting of slave address and rbw), the first bytes match. the state of this bit is changed from ??to ??by executing a write instruction to the i 2 c data shift register (address 00f6 16 ). (4) bit 3: arbitration lost ? detecting flag (al) in the master transmission mode, when a device other than the mi- crocomputer sets the sda to ?,?arbitration is judged to have been lost, so that this bit is set to ?.?at the same time, the trx bit is set to ?,?so that immediately after transmission of the byte whose arbitra- tion was lost is completed, the mst bit is set to ?.?when arbitration is lost during slave address transmission, the trx bit is set to ??and the reception mode is set. consequently, it becomes possible to re- ceive and recognize its own slave address transmitted by another master device. ? arbitration lost: the status in which communication as a master is disabled. (5) bit 4: i 2 c-bus interface interrupt request bit (pin) this bit generates an interrupt request signal. each time 1-byte data is transmitted, the state of the pin bit changes from ??to ?.?at the same time, an interrupt request signal is sent to the cpu. the pin bit is set to ??in synchronization with a falling edge of the last clock (including the ack clock) of an internal clock and an interrupt re- quest signal occurs in synchronization with a falling edge of the pin bit. when the pin bit is ?,?the scl is kept in the ??state and clock generation is disabled. figure 8.6.9 shows an interrupt request sig- nal generating timing chart. the pin bit is set to ??in any one of the following conditions. executing a write instruction to the i 2 c data shift register (address 00f6 16 ). when the eso bit is ? at reset the conditions in which the pin bit is set to ??are shown below: immediately after completion of 1-byte data transmission (includ- ing when arbitration lost is detected) immediately after completion of 1-byte data reception in the slave reception mode, with als = ??and immediately after completion of slave address or general call address reception in the slave reception mode, with als = ??and immediately after completion of address data reception (6) bit 5: bus busy flag (bb) this bit indicates the status of the bus system. when this bit is set to ?,?this bus system is not busy and a start condition can be gen- erated. when this bit is set to ?,?this bus system is busy and the occurrence of a start condition is disabled by the start condition duplication prevention function (see note). this flag can be written by software only in the master transmission mode. in the other modes, this bit is set to ??by detecting a start condition and set to ??by detecting a stop condition. when the eso bit of the i 2 c control register (address 00f9 16 ) is ??at reset, the bb flag is kept in the ??state. (7) bit 6: communication mode specification bit (transfer direction specification bit: trx) this bit decides the direction of transfer for data communication. when this bit is ?,?the reception mode is selected and the data of a trans- mitting device is received. when the bit is ?,?the transmission mode is selected and address data and control data are output into the sda in synchronization with the clock generated on the scl. when the als bit of the i 2 c control register (address 00f9 16 ) is ??in the slave reception mode, the trx bit is set to ??(transmit) if the ___ least significant bit (r/w bit) of the address data transmitted by the ___ master is ?.?when the als bit is ??and the r/w bit is ?,?the trx bit is cleared to ?? (receive). the trx bit is cleared to ??in one of the following conditions. when arbitration lost is detected. when a stop condition is detected. when occurence of a start condition is disabled by the start condition duplication prevention function (note). when mst = ??and a start condition is detected. when mst = ??and ack non-return is detected. at reset
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 37 of 139 rej03b0128-0100z (8) bit 7: communication mode specification bit (master/slave specification bit: mst) this bit is used for master/slave specification in data communica- tions. when this bit is ?,?the slave is specified, so that a start condition and a stop condition generated by the master are received, and data communication is performed in synchronization with the clock generated by the master. when this bit is ?,?the master is specified and a start condition and a stop condition are gener- ated, and also the clocks required for data communication are gen- erated on the scl. the mst bit is cleared to ??in any of the following conditions. immediately after completion of 1-byte data transmission when arbitration lost is detected when a stop condition is detected. when occurence of a start condition is disabled by the start condition duplication prevention function (note). at reset fig. 8.6.8 i 2 c status register b 7 b3 b2 b 1 b0 i 2 c status re g ister ( s 1) [address 00f8 16 ] i 2 r 0 3 4 5 6, 7 b7 b6 0 0 : slave recieve mode 0 1 : slave transmit mode 1 0 : master recieve mode 1 1 : master transmit mode 1 2 0 0 0 1 0 b name functions after reset communication mode specification bits (trx, mst) 0 : bus free 1 : bus busy bus busy flag (bb) 0 : interrupt request issued 1 : no interrupt request issued i 2 c-bus interface interrupt request bit (pin) 0 : not detected 1 : detected arbitration lost detecting flag (al) (see note) 0 : address mismatch 1 : address match slave address comparison flag (aas) (see note) 0 : no general call detected 1 : general call detected general call detecting flag (ad0) (see note) 0 : last bit = ?0 ? 1 : last bit = ?1 ? last receive bit (lrb) (see note) note : these bits and flags can be read out, but cannnot be written. indeterminate 0 w r r ? r? r? r? rw rw rw (see note) (see note) (see note) (see note) fig. 8.6.9 interrupt request signal generation timing sc l pin i i c i r q note: the start condition duplication prevention function disables the start condition generation, bit counter reset, and scl output, when the follow- ing condition is satisfied: a start condition is set by another master device.
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 38 of 139 rej03b0128-0100z 8.6.6 start condition generation method when the eso bit of the i 2 c control register (address 00f9 16 ) is ?, execute a write instruction to the i 2 c status register (address 00f8 16 ) to set the mst, trx and bb bits to ?.? a start condition will then be generated. after that, the bit counter becomes ?00 2 ?and an scl is output for 1 byte. the start condition generation timing and bb bit set timing are different in the standard clock mode and the high- speed clock mode. refer to figure 8.6.10 for the start condition generation timing diagram, and table 8.6.2 for the start condition/ stop condition generation timing table. fig. 8.6.10 start condition generation timing diagram i 2 c stat us register write sig nal hold time setup time s c l s d a b b f l a g s e t t i m e f o r b b f l a g 8.6.7 stop condition generation method when the eso bit of the i 2 c control register (address 00f9 16 ) is ?, execute a write instruction to the i 2 c status register (address 00f8 16 ) to set the mst bit and the trx bit to ??and the bb bit to ?? a stop condition will then be generated. the stop condition generation tim- ing and the bb flag reset timing are different in the standard clock mode and the high-speed clock mode. refer to figure 8.6.11 for the stop condition generation timing diagram, and table 8.6.2 for the start condition/stop condition generation timing table. fig. 8.6.11 stop condition generation timing diagram t able 8.6.2 start condition/stop condition generation tim- ing table item setup time (start condition) setup time (stop condition) hold time set/reset time for bb flag standard clock mode 5.0 s (20 cycles) 4.25 s (17 cycles) 5.0 s (20 cycles) 3.0 s (12 cycles) high-speed clock mode 2.5 s (10 cycles) 1.75 s (7 cycles) 2.5 s (10 cycles) 1.5 s (6 cycles) note: absolute time at = 4 mhz. the value in parentheses denotes the number of cycles. = 8.95/2 mhz at fscin = 3.58 mhz = 8.86/2 mhz at fscin = 4.43 mhz i 2 c stat us register write sig nal h o l d t i m e s e t u p t i m e scl sda bb flag r e se t t i m e f o r b b f l a g
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 39 of 139 rej03b0128-0100z 8.6.8 start/stop condition detect conditions the start/stop condition detect conditions are shown in figure 8.6.12 and table 8.6.3. only when the 3 conditions of table 8.6.3 are satisfied, a start/stop condition can be detected. note: when a stop condition is detected in the slave mode (mst = 0), an interrupt request signal ?icirq?is generated to the cpu. fig. 8.6.12 start condition/stop condition detect timing diagram standard clock mode 6.5 s (26 cycles) < scl release time 3.25 s (13 cycles) < setup time 3.25 s (13 cycles) < hold time high-speed clock mode 1.0 s (4 cycles) < scl release time 0.5 s (2 cycles) < setup time 0.5 s (2 cycles) < hold time t able 8.6.3 start condition/stop condition detect conditions note: absolute time at = 4 mhz. the value in parentheses denotes the num- ber of cycles. = 8.95/2 mhz at fscin = 3.58 mhz = 8.86/2 mhz at fscin = 4.43 mhz h o l d t i m e s e t u p t i m e s c l s d a ( s t a r t c o n d i t i o n ) sda (stop condition) s c l r e l e a s e t i m e hold time s e t u p t i m e 8.6.9 address data communication there are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. the respective ad- dress communication formats are described below. (1) 7-bit addressing format to support the 7-bit addressing format, set the 10bit sad bit of the i 2 c control register (address 00f9 16 ) to ?.?the first 7-bit address data transmitted from the master is compared with the high-order 7- bit slave address stored in the i 2 c address register (address 00f7 16 ). at the time of this comparison, address comparison of the rbw bit of the i 2 c address register (address 00f7 16 ) is not made. for the data transmission format when the 7-bit addressing format is selected, refer to figure 8.6.13, (1) and (2). (2) 10-bit addressing format to support the 10-bit addressing format, set the 10bit sad bit of the i 2 c control register (address 00f9 16 ) to ?.?an address comparison is made between the first-byte address data transmitted from the master and the 7-bit slave address stored in the i 2 c address register (address 00f7 16 ). at the time of this comparison, an address com- parison is performed between the rbw bit of the i 2 c address regis- ter (address 00f7 16 ) and the r/w bit, which is the last bit of the address data transmitted from the master. in the 10-bit addressing mode, the r/w bit, not only specifies the direction of communication for control data but is also processed as an address data bit. when the first-byte address data matches the slave address, the aas bit of the i 2 c status register (address 00f8 16 ) is set to ?.?after the second-byte address data is stored into the i 2 c data shift register (address 00f6 16 ), perform an address comparison between the sec- ond-byte data and the slave address by software. when the address data of the 2nd byte matches the slave address, set the rbw bit of the i 2 c address register (address 00f7 16 ) to ??by software. this processing can match the 7-bit slave address and r/w data, which are received after a restart condition is detected, with the value of the i 2 c address register (address 00f7 16 ). for the data transmis- sion format when the 10-bit addressing format is selected, refer to figure 8.6.13, (3) and (4).
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 40 of 139 rej03b0128-0100z 8.6.10 example of master transmission an example of master transmission in the standard clock mode, at the scl frequency of 100 khz with the ack return mode enabled, is shown below. ? set a slave address in the high-order 7 bits of the i 2 c address register (address 00f7 16 ) and ??in the rbw bit. ? set the ack return mode and scl = 100 khz by setting ?5 16 ?in the i 2 c clock control register (address 00fa 16 ). ? set ?0 16 ?in the i 2 c status register (address 00f8 16 ) and hold the scl at high. ? set a communication enable status by setting ?8 16 ?in the i 2 c control register (address 00f9 16 ). ? set the address data of the destination of transmission in the high- order 7 bits of the i 2 c data shift register (address 00f6 16 ) and set ??in the least significant bit. ? set ?0 16 ?in the i 2 c status register (address 00f8 16 ) to generate a start condition. at this time, an scl for 1 byte and an ack clock automatically occurs. ? set transmit data in the i 2 c data shift register (address 00f6 16 ). at this time, an scl and an ack clock automatically occurs. ? when transmitting control data of more than 1 byte, repeat step ? . ? set ?0 16 ?in the i 2 c status register (address 00f8 16 ). after this, if ack is not returned or transmission ends, a stop condition will be generated. 8.6.11 example of slave reception an example of slave reception in the high-speed clock mode, at the scl frequency of 400 khz, with the ack non-return mode enabled while using the addressing format, is shown below. ? set a slave address in the high-order 7 bits of the i 2 c address register (address 00f7 16 ) and ??in the rbw bit. ? set the ack non-return mode and scl = 400 khz by setting ?5 16 in the i 2 c clock control register (address 00fa 16 ). ? set ?0 16 ?in the i 2 c status register (address 00f8 16 ) and hold the scl at high. ? set a communication enable status by setting ?8 16 ?in the i 2 c control register (address 00f9 16 ). ? when a start condition is received, an address comparison is executed. ? ?hen all transmitted address are??(general call): ad0 of the i 2 c status register (address 00f8 16 ) is set to ??and an interrupt request signal occurs. ?hen the transmitted addresses match the address set in ? : ass of the i 2 c status register (address 00f8 16 ) is set to ??and an interrupt request signal occurs. ?n the cases other than the above: ad0 and aas of the i 2 c status register (address 00f8 16 ) are set to ??and no interrupt request signal occurs. ? set dummy data in the i 2 c data shift register (address 00f6 16 ). ? when receiving control data of more than 1 byte, repeat step ? . ? when a stop condition is detected, the communication ends.
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 41 of 139 rej03b0128-0100z fig. 8.6.13 address data communication format ss l a v e a d d r e s s a d a t aa d a t aa / a p r / w 7 b i t s? 0 ?1 t o 8 b i t s1 to 8 bits ss l a v e a d d r e s s a d a t a ad a t a ap 7 b i t s? 1 ?1 t o 8 b i t s1 to 8 bits ( 1 ) a m a s t e r - t r a n s m i t t e r t r a n s m i t s d a t a t o a s l a v e - r e c e i v e r s s l a v e a d d r e s s 1 s t 7 b i t s a a d a t a 7 b i t s? 0 ?8 b i t s1 to 8 bits (2) a master-receiver receives data from a slave-transmitte r s l a v e a d d r e s s 2 n d b y t e a d a t aa / a p 1 t o 8 b i t s s s l a v e a d d r e s s 1 s t 7 b i t s a a 7 b i t s? 0 ?8 b i t s7 bit s (3) a master-transmitter transmits data to a slave-receiver with a 10-bit address s l a v e a d d r e s s 2 n d b y t e data 1 to 8 bits sr slav e address 1st 7 bits a data a p 1 t o 8 b i t s ?1? (4) a master-receiver receives data from a slave-transmitter with a 10-bit address s:st art conditio np : stop condition a:ack bit r/w : read/write bit sr : restart c ondit ion from ma ster to slave from sl ave to master r / w r / w r/w r/w 8.6.12 precautions when using multi-master i 2 c-bus interface (1) read-modify-write instruction precautions for executing the read-modify-write instructions, such as seb, and clb, is for each register of the multi-master i 2 c-bus interface are described below. ? 2 c data shift register (s0) when executing the read-modify-write instruction for this register during transfer, data may become an arbitrary value. ? 2 c address register (s0d) when the read-modify-write instruction is executed for this register at detection of the stop condition, data may become an arbitrary ______ value. because hardware changes the read/write bit (rbw) at the above timing. ? 2 c status register (s1) do not execute the read-modify-write instruction for this register because all bits of this register are changed by hardware. ? 2 c control register (s1d) when the read-modify-write instruction is executed for this register at detection of the start condition or at completion of the byte transfer, data may become an arbitrary value because hardware changes the bit counter (bc0?c2) at the above timing. ? 2 c clock control register (s2) the read-modify-write instruction can be executed for this register. (2) start condition generating procedure us- ing multi-master procedure example (the necessary conditions for the procedure are described in to below). lda (take out slave address value) sei (interrupt disabled) bbs 5,s1,busbusy (bb flag confirmation and branch pro cess) busfree: sta s0 (write slave address value) ldm #$f0, s1 (trigger start condition generation) cli (interrupt enabled) busbusy: cli (interrupt enabled) use ?ta,? ?tx?or ?ty?of the zero page addressing instruc- tion for writing the slave address value to the i 2 c data shift register. use ?dm?instruction for setting trigger of start condition gen- eration. write the slave address value of and set trigger of start con- dition generation as in continuously, as shown in the procedure example. disable interrupts during the following three process steps: ?bb flag confirmation ?write slave address value ?trigger of start condition generation when the condition of the bb flag is bus busy, enable interrupts immediately.
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 42 of 139 rej03b0128-0100z (3) restart condition generation procedure ? procedure example (the necessary conditions for the procedure are described in ? to ? below.) execute the following procedure when the pin bit is ?. ldm #$00, s1 (select slave receive mode) lda ? t ake out slave address value) sei (interrupt disabled) st as 0( w rite slave address value) ldm #$f0, s1 (trigger restart condition generation) cli (interrupt enabled) ? select the slave receive mode when the pin bit is ?.?do not write ??to the pin bit. neither ??nor ??is specified for the writing to the bb bit. the trx bit becomes ??and the sda pin is released. ? the scl pin is released by writing the slave address value to the i 2 c data shift register. use ?ta,??tx?or ?ty?of the zero page addressing instruction for writing. ? use ?dm?instruction for setting trigger of restart condition generation. ? w rite the slave address value of ? and set trigger of restart condition generation of ? continuously, as shown in the procedure example. ? disable interrupts during the following two process steps: ?write slave address value ?trigger restart condition generation (4) stop condition generation procedure ? procedure example (the necessary conditions for the procedure are described in ? to ? below.) sei (interrupt disabled) ldm #$c0, s1 (select master transmit mode) nop (set nop) ldm #$d0, s1 (trigger stop condition generation) cli (interrupt enabled) ? write ??to the pin bit when master transmit mode is selected. ? execute ?op?instruction after master transmit mode is set. also, set trigger of stop condition generation within 10 cycles after se- lecting the master trasmit mode. ? disable interrupts during the following two process steps: ?select master transmit mode ?trigger stop condition generation (5) writing to i 2 c status register do not execute an instruction to set the pin bit to ??from ??and an instruction to set the mst and trx bits to ??from ??simultaneously as it may cause the scl pin the sda pin to be released after about one machine cycle. also, do not execute an instruction to set the mst and trx bits to ??from ??when the pin bit is ?,?as it may cause the same problem. (6) process after stop condition generation do not write data in the i 2 c data shift register s0 and the i 2 c status register s1 until the bus busy flag bb becomes ??after generating the stop condition in the master mode. doing so may cause the stop condition waveform from being generated normally. reading the registers does not cause the same problem.
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 43 of 139 rej03b0128-0100z 8.7 pwm output function this microcomputer is equipped with five 8-bit pwms (pwm0 pwm4). pwm0?wm4 have the same circuit structure, an 8-bit reso- lution with minimum resolution bit width of 4 s (for f(x in ) = 8 mhz) and repeat period of 1024 s (for f(x in ) = 8 mhz). f(x in ): 8.95 mhz at fscin = 3.58 mhz min. resolution bit width: 4 s ? 8/8.95 = 3.58 s repeat period:1024 s ? 8/8.95 = 915 s f(x in ): 8.86 mhz at fscin = 4.43 mhz min. resolution bit width: 4 s ? 8/8.86 = 3.61 s repeat period: 1024 s ? 8/8.86 = 925 s. figure 8.7.1 shows the pwm block diagram. the pwm timing gen- erating circuit applies individual control signals to pwm0?wm4 us- ing f(x in ) divided by 2 as a reference signal. 8.7.1 data setting when outputting pwm0?wm4, set 8-bit output data to the pwmi register (i means 0 to 4; addresses 0200 16 to 0204 16 ). 8.7.2 transmitting data from register to pwm circuit data transfer from the 8-bit pwm register to the 8-bit pwm circuit is executed when writing data to the register. the signal output from the 8-bit pwm output pin corresponds to the contents of this register. 8.7.3 operating of 8-bit pwm the following explains the pwm operation. first, set bit 0 of pwm mode register 1 (address 0208 16 ) to ??(at reset, bit 0 is already set to ??automatically), so that the pwm count source is supplied. pwm0?wm4 are also used as pins p0 0 ?0 4 . set the correspond- ing bits of the port p0 direction register to ??(output mode). and select each output polarity by bit 3 of pwm mode register 1 (address 0208 16 ). then, set bits 4 to 0 of pwm mode register 2 (address 0209 16 ) to ??(pwm output). the pwm waveform is output from the pwm output pins by setting these registers. figure 8.7.2 shows the 8-bit pwm timing. one cycle (t) is com- posed of 256 (2 8 ) segments. 8 kinds of pulses, relative to the weight of each bit (bits 0 to 7), are output inside the circuit during 1 cycle. refer to figure 8.7.2 (a). the 8-bit pwm outputs a waveform which is the logical sum (or) of pulses corresponding to the contents of bits 0 to 7 of the 8-bit pwm register. several examples are shown in figure 8.7.2 (b). 256 kinds of output (high area: 0/256 to 255/256) are selected by changing the contents of the pwm register. an en- tirely high section cannot be output, i.e. 256/256. 8.7.4 output after reset at reset, the output of ports p0 0 ?0 4 is in the high-impedance state, and the contents of the pwm register and the pwm circuit are unde- fined. note that after reset, the pwm output is undefined until setting the pwm register.
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 44 of 139 rej03b0128-0100z fig. 8.7.1 pwm block diagram 1/2 pm10 x in b7 b0 8 pm13 p0 0 pm20 d0 0 pwm0 p0 1 pm21 d0 1 pwm1 p0 2 pm22 d0 2 pwm2 p0 3 pm23 d0 3 pwm3 p0 4 pm24 d0 4 pwm4 pm1 pm2 p0 d0 : pwm mode register 1 (address 0208 16 ) : pwm mode register 2 (address 0209 16 ) : po rt p0 register (address 00c0 16 ) : po rt p0 direction register (address 00c1 16 ) selection gate: connected to b lack side at reset. is as same contents with the others. pwm1 register (address 0201 16 ) pwm2 register (address 0202 16 ) pwm3 register (address 0203 16 ) pwm4 register (address 0204 16 ) pwm timing generating circuit data bus pwm0 register (address 0200 16 ) 8-bit pwm circuit inside of
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 45 of 139 rej03b0128-0100z fig. 8.7.2 pwm timing (a) pulses showing the weight of each bi t 1357 9 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 255 4122 028364 452 6068 768492100108 116 124 132 140 148 156 164 172 180 188 196 2 04 212 220 228 236 244 252 8 16 48 80 112 144 176 208 240 24 40 56 72 88 104 120 136 152 168 184 200 216 232 248 32 96 160 224 64 192 bit 7 2610 14 18 22 26 30 34 38 42 46 50 54 58 62 66 70 74 78 82 86 90 94 98 102 106 110 114 118 122 126 130 134 138 142 146 150 154 158 162 166 170 174 178 182 186 190 194 198 202 206 210 214 218 222 226 230 234 238 242 246 250 254 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 128 bit 0 pwm output t = 4 s t = 1024 s f(x in ) = 8 mhz (b) example of 8-bit pwm t 00 16 (0) 01 16 (1) 18 16 (24) ff 16 (255) t = 256 t
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 46 of 139 rej03b0128-0100z fig. 8.7.3 pwm mode register 1 fig. 8.7.4 pwm mode register 2 b 7 b6 b 5 b 4 b 3 b 2 b 1 b 0 pwm mode register 1 (pm1) [address 0208 16 ] b a f t e r r e s e t rw p w m m o d e r e g i s t e r 1 0 1 , 2 3 0 n a m ef unctions p w m o u t p u t p o l a r i t y s e l e c t i o n b i t ( p m 1 3 ) i n d e t e r m i n a t e 0 n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y r w r rw p w m c o u n t s s o u r c e s e l e c t i o n b i t ( p m 1 0 ) 0 : c o u n t s o u r c e s u p p l y 1 : c o u n t s o u r c e s t o p 4 to 7 i n d e t e r m i n a t e n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . r b7 b6 b5 b4 b3 b2 b1 b0 pwm mode register 2 (pm2) [address 0209 16 ] b after reset r w pwm mode register 2 0 1 2 3 4 0 name functions p0 0 /pwm0 output selection bit (pm20) 0 : p0 0 output 1 : pwm0 output p0 2 /pwm2 output selection bit (pm22) 0 : p0 2 output 1 : pwm2 output p0 3 /pwm3 output selection bit (pm23) 0 : p0 3 output 1 : pwm3 output p0 4 /pwm4 output selection bit (pm24) 0 : p0 4 output 1 : pwm4 output 5 to 7 fix these bits to ?. p0 1 /pwm1 output selection bit (pm21) 0 : p0 1 output 1 : pwm1 output 0 0 0 0 0 rw rw rw rw rw rw 00 0
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 47 of 139 rej03b0128-0100z 8.8 a-d comparator the a-d comparator consists of a 7-bit d-a converter and a com- parator. the a-d comparator block diagram is shown in figure 8.8.1. the reference voltage ? ref ?for d-a conversion is set by bits 0 to 6 of a-d control register 2 (address 00ed 16 ). the comparison result of the analog input voltage and the reference voltage ? ref ?is stored in bit 4 of a-d control register 1 (address 00ec 16 ). for a-d comparison, set ??to corresponding bits of the direction register to use ports as analog input pins. write the data to select analog input pins for bits 0 to 2 of a-d control register 1 and write the digital value corresponding to v ref to be compared to bits 0 to 4 of a-d control register 2. the voltage comparison is started by writing to a-d control register 2, and it is completed after 16 machine cycles (nop instruction ? 8). fig. 8.8.1 a-d comparator block diagram a-d control register 1 bits 0 to 2 comparator control data bus bit 4 switch tree a-d control register 2 resistor ladder compa- r ator analog signal s witch bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 a-d control register 1 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 48 of 139 rej03b0128-0100z fig. 8.8.2 a-d control register 1 b7 b6 b5 b4 b3 b2 b1 b0 a-d control register 1 (ad1) [address 00ec 16 ] b after reset rw a-d control register 1 0 to 2 analog input pin selection bits (adc10 to adc12) name functions b2 b1 b0 0 0 0 : ad1 0 0 1 : ad2 0 1 0 : ad3 0 1 1 : ad4 1 0 0 : ad5 1 0 1 : ad6 ad7 ad8 1 1 0 : 1 1 1 : 4 storage bit of comparison result (adc14) 0: input voltage < reference voltage 1: input voltage > reference voltage 0 indeterminate 0 3t his bit is a write disable bit. when this bit is read out, the value is ?. rw r r 0 5 to 7 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are ?. r fig. 8.8.3 a-d control register 2 b7 b6 b5 b4 b3 b2 b1 b0 a-d control register 2 (ad2) [address 00ed 16 ] b after reset r w a-d control register 2 0 to 6 7 0 0 name functions d-a converter set bits (adc20 to adc25) b0 b1 b2 b3 b4 b5 nothing is assigned. this bit is a write disable bit. when these bits are reed out, the values are ?0. 1 000000 00000 0 0000 0 0 111 1 1 11111 1 1 b6 1 0 0 0 1 1 1111 1 rw r : 3/256vcc : 5/256vcc : 251/256vcc : 253/256vcc : 255/256vcc : 1/256vcc
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 49 of 139 rej03b0128-0100z fig. 8.9.2 rom correction enable register fig. 8.9.1 rom correction address registers 8.9 rom correction function this can correct program data in the rom. up to 2 addresses can be corrected; a program for correction is stored in the rom correction vector in the ram as the top address. there are 2 vectors for rom correction: v ector 1 : address 0300 16 v ector 2 : address 0320 16 set the address of the rom data to be corrected into the rom cor- rection address register. when the value of the counter matches the rom data address in the top address of the rom correction vector, the main program branches to the correction program stored in the rom memory. to return from the correction program to the main program, the op code and operand of the jmp instruction (total of 3 bytes) are necessary at the end of the correction program. the rom correction function is controlled by the rom correction enable register. notes 1: specify the first address (op code address) of each instruction as the rom correction address. 2: use the jmp instruction (total of 3 bytes) to return from the correction program to the main program. 3: do not set the same rom correction address to both vectors 1 and 2. 020a 16 rom correction address 1 (high-order) 020b 16 rom correction address 1 (low-order) 020c 16 rom correction address 2 (high-order) 020d 16 rom correction address 2 (low-order) b7 b6 b5 b4 b3 b2 b1 b0 rom correction enable register (rcr) [address 020e 16 ] b after reset rw rom correction enable register 0 vector 1 enable bit (rc0) name functions 0: disabled 1: enabled 1 vector 2 enable bit (rc1) 0: disabled 1: enabled 2 to 7 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are ?.? 0 0 0 rw rw r
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 50 of 139 rej03b0128-0100z 8.10 data slicer this microcomputer includes the data slicer function for the closed caption decoder (referred to as the ccd). this function takes out the caption data superimposed in the vertical blanking interval of a com- posite video signal. a composite video signal, which makes the sync chips polarity negative, is input to the cv in pin. when the data slicer function is not used, the data slicer circuit and the timing signal generating circuit can be cut off by setting bit 0 of data slicer control register 1 (address 00e0 16 ) to ?.?these settings support the low-power dissipation. fig. 8.10.1 data slicer block diagram composite video signal 1 m ? sync pulse counter register (address 00e9 16 ) data slicer control register 2 (address 00e1 16 ) data slicer control register 1 (address 00e0 16 ) clock run-in defect register (address 00e4 16 ) caption position register (address 00e6 16 ) data clock position register (address 00e5 16 ) interrupt request generating circuit data slicer interrupt request synchronizing signal counter synchronizing separation circuit sync slice circuit clamping circuit low-pass filter timing signal generating circuit clock run-in determination circuit data slice line specification circuit start bit detecting circuit data clock generating circuit 16-bit shift register caption data register 1 (address 00e2 16 ) caption data register 2 (address 00e3 16 ) data bus comparator 0.1 f 470 ? 560 pf cv in 1 f 1 k ? 200 pf h sync hlf + reference voltage generating circuit v hold 1000 pf high-order low-order data slicer on/off caption data register 4 (address 00cf 16 ) caption data register 3 (address 00ce 16 ) external circuit note : make the length of wiring which is connected to v hold , hlf, and cv in pin as short as possible so that a leakage current may not be generated when mounting a resistor or a capacitor on each pin.
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 51 of 139 rej03b0128-0100z hlf v hold cv in open open leave hlf pin open. leave v hold pin open. pull-down cv in pin to v ss through a resistor of 5 k ? or more. 5 k ? or more 24 25 26 connect the same external circuit as when using data slicer to hlf pin. leave v hold pin open. pull-up cv in to v cc through a resistor of 5 k ? or more. v hold cv in open 5 k ? or more hlf 1 k ? 200pf 1 f 24 25 26 8.10.1 notes when not using data slicer when bit 0 of data slicer control register 1 (address 00e0 16 ) is ?, terminate the pins as shown in figure 8.10.2. fig. 8.10.2 termination of data slicer input/output pins when data slicer circuit and timing generating circuit are in off stat e when both bits 0 and 2 of data slicer control register 1 (address 00e0 16 ) are ?,?terminate the pins as shown in figure 8.10.3. fig. 8.10.3 termination of data slicer input/output pins when timing signal generating circuit is in on state
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 52 of 139 rej03b0128-0100z figures 8.10.4 and 8.10.5 the data slicer control registers. fig. 8.10.4 data slicer control register 1 fig. 8.10.5 data slicer control register 2 b 7b 6b 5b 4b 3b 2b 1b 0 d a t a s l i c e r c o n t r o l r e g i s t e r 1 ( d s c 1 ) [ a d d r e s s 0 0 e 0 1 6 ] d a t a s l i c e r c o n t r o l r e g i s t e r 1 00 rw 0rw 2r e f e r e n c e c l o c k s o u r c e s e l e c t i o n b i t ( d s c 1 2 ) 0 : v i d e o s i g n a l 1 : h s y n c s i g n a l 0r w 0rw 0rw 11 0 : s t o p p e d 1 : o p e r a t i n g d a t a s l i c e r a n d t i m i n g s i g n a l g e n e r a t i n g c i r c u i t c o n t r o l b i t ( d s c 1 0 ) f i x t h e s e b i t s t o 0 . 3 , 4 000 10 : f 2 1 : f 1 s e l e c t i o n b i t o f d a t a s l i c e r e f e r e n c e v o l t a g e g e n e r a t i n g f i e l d ( d s c 1 1 ) f i x t h e s e b i t s t o 1 . 5 , 6 d e f i n i t i o n o f f i e l d s 1 ( f 1 ) a n d 2 ( f 2 ) h s e p v s e p f 1 : h s e p v s e p f 2 : b a f t e r r e s e t r w n a m ef u n c t i o n s 0rw f i x t h i s b i t t o 0 . 7 b7 b6 b5 b4 b3 b2 b1 b0 data slicer control register 2 (dsc2) [address 00e1 16 ] rw data slicer control register 2 indeterminate indeterminate indeterminate indeterminate indeterminate r 1 0 r w r r 01 0: data is not latched yet and a clock-run-in is not determined. 1: data is latched and a clock-run-in is determined. caption data latch completion flag 1 (dsc20) fix this bit to ?. 2 read-only test bit 00: f2 1: f1 field determination flag(dsc23) 0: method (1) 1: method (2) vertical synchronous signal (v sep ) generating method selection bit (dsc24) 0 rw 50 : match 1: mismatch v-pulse shape determination flag (dsc25) r 6 4 0 r w fix this bit to ?. b 1 after reset functions name definition of fields 1 (f1) and 2 (f2) h sep v sep f1: h sep v se p f2 : r 7 read-only test bit
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 53 of 139 rej03b0128-0100z 8.10.2 clamping circuit and low-pass filter the clamp circuit clamps the sync chip part of the composite video signal input from the cv in pin. the low-pass filter attenuates the noise of the clamped composite video signal. the cv in pin to which com- posite video signal is input requires an external capacitor (0.1 f) coupling. pull down the cv in pin with a resistor of hundreds of kilo- ohms to 1 m ? . in addition, we recommend installing a simple low- pass filter externally, using a resistor and a capacitor at the cv in pin (refer to figure 8.10.1). 8.10.3 sync slice circuit this circuit takes out a composite sync signal from the output signal of the low-pass filter. 8.10.4 synchronous signal separation circuit this circuit separates a horizontal synchronous signal and a vertical synchronous signal from the composite sync signal taken out in the sync slice circuit. (1) horizontal synchronous signal (h sep ) a one-shot horizontal synchronizing signal hsep is generated at the falling edge of the composite sync signal. (2) vertical synchronous signal (v sep ) as a v sep signal generating method, it is possible to select one of the following 2 methods by using bit 4 of data slicer control regis- ter 2 (address 00e1 16 ). ?ethod 1 the low level width of the composite sync signal is measured. if this width exceeds a certain time, a v sep signal is generated in synchronization with the rising of the timing signal immediately after this low level. ?ethod 2 the low level width of the composite sync signal is measured. if this width exceeds a certain time, it is detected whether a falling of the composite sync sig- nal exits or not in the low level period of the timing signal immediately after this low level. if a falling exists, a v sep signal is generated in synchronization with the rising of the timing signal (refer to figure 8.10.6). figure 8.10.6 shows a v sep generating timing. the timing signal shown in the figure is generated from the reference clock which the timing generating circuit outputs. reading bit 5 of data slicer control register 2 permits determinating the shape of the v-pulse portion of the composite sync signal. as shown in figure 8.10.7, when the a level matches the b level, this bit is ?.?in the case of a mismatch, the bit is ?. fig. 8.10.6 vsep generating timing (method 2) c o m p o s i t e s t i m i n g s i g n a l v sep si gnal m e a s u r e l o w p e r i o d a v sep si gnal is generated at a rising of the timing signal imm ediately after the low level width of the composite sync signal exceed s a certai n time.
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 54 of 139 rej03b0128-0100z 8.10.5 timing signal generating circuit this circuit generates a reference clock which is 832 times as large as the horizontal synchronous signal frequency. it also generates various timing signals on the basis of the reference clock, horizontal synchronous signal and vertical synchronizing signal. the circuit operates by setting bit 0 of data slicer control register 1 (address 00e0 16 ) to ?. the reference clock can be used as a display clock for the osd function in addition to the data slicer. the h sync signal can be used as a count source instead of the composite sync signal. however, when the h sync signal is selected, the data slicer cannot be used. a count source of the reference clock can be selected by bit 2 of data slicer control register 1 (address 00e0 16 ). for pins hlf, connect a resistor and a capacitor as shown in figure 8.10.1. make the length of wiring which is connected to these pins as short as possible to prevent a leakage current from being generated. note: it takes a few tens of milliseconds until the reference clock becomes stable after the data slicer and the timing signal generating circuit are started. in this period, various timing signals, h sep signals and v sep sig- nals become unstable. for this reason, take stabilization time into con- sideration when programming. fig. 8.10.7 determination of v-pulse waveform composite sync signal ab 0 1 1 bit 5 of dsc2
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 55 of 139 rej03b0128-0100z 8.10.6 data slice line specification circuit (1) specification of data slice line this circuit determines the lines on to which caption data is super- imposed. data can be sliced for line 21 and one arbitrary line in both field (2 lines total per field). the caption position register (ad- dress 00e6 16 ) is used for each setting (refer to table 8.10.1). the counter is reset at the falling edge of v sep and is incremented by 1 every h sep pulse. when the counter value matches the value specified by bits 4 to 0 of the caption position register, this h sep is sliced. the values of ?0 16 ?to ?f 16 ?can be set in the caption position register (when setting only one arbitrary line). figure 8.10.8 shows the signals in the vertical blanking interval. figure 8.10.9 shows the structure of the caption position register. (2) specification of line to set slice voltage t able 8.10.1 shows which field and line generates the reference slice voltage for the clock run-in pulse of each line. the field to generate slice voltage is specified by bit 1 of data slicer control register 1. the line to generate slice voltage for one field is speci- fied by bits 6 and 7 of the caption position register (refer to table 8.10.1). fig. 8.10.8 signals in vertical blanking interval (3) field determination the field determination flag can be read out by bit 3 of data slicer control register 2. this flag charges at the falling edge of v sep . video signal vertical blanking interval composite video signal count value to be set in the caption position register (?f 16 ?in this case) h sep v sep h sep magnified drawing clock run-in start bit + 16-bit data start bit window for deteminating clock-run-in composite video signal line 21 1 appropriate line is set by the caption position register (when setting line 19)
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 56 of 139 rej03b0128-0100z fig. 8.10.9 caption position register field and line to generate slice voltage ? ield specified by bit 1 of dsc1 line 21 (total 1 line) ? ield specified by bit 1 of dsc1 ? line specified by bits 4 to 0 of cps (total 1 line) (see note 3) ? ield specified by bit 1 of dsc1 line 21 (total 1 line) ? ield specified by bit 1 of dsc1 line 21 and a line specified by bits 4 to 0 of cps (total 2 lines) (see note 2) field and line to be sliced data both fields of f1 and f2 line 21 and a line specified by bits 4 to 0 of cps (total 2 lines) (see note 2) both fields of f1 and f2 ? line specified by bits 4 to 0 of cps (total 1 line) (see note 3) both fields of f1 and f2 line 21 (total 1 line) both fields of f1 and f2 line 21 and a line specified by bits 4 to 0 of cps (total 2 lines) (see note 2) cps b7 0 0 1 1 b6 0 1 0 1 notes 1: dsc1 is data slicer control register 1. cps is caption position register. 2: set ?0 16 ?to ?0 16 ?to bits 4 to 0 of cps. 3: set ?0 16 ?to ?f 16 ?to bits 4 to 0 of cps. t able 8.10.1 specification of data slice line b7 b6 b5 b4 b3 b2 b1 b0 caption position register (cps) [address 00e6 16 ] caption position registe r 0 to 4 0 r w 0 r w caption position bits(cps0 to cps4) 6, 7 refer to the corresponding table (table 8.10.1). slice line mode specification bits (in 1 field) (cps6, cps7) 5 0: data is not latched yet and a clock-run-in is not determined. 1: data is latched and a clock-run-in is determined. caption data latch completion flag 2 (cps5) indeterminate r after reset functions na b m e r w
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 57 of 139 rej03b0128-0100z 8.10.7 reference voltage generating circuit and comparator the composite video signal clamped by the clamping circuit is input to the reference voltage generating circuit and the comparator. (1) reference voltage generating circuit this circuit generates a reference voltage (slice voltage) by us- ing the amplitude of the clock run-in pulse in the line specified by the data slice line specification circuit. connect a capacitor be- tween the v hold pin and the v ss pin, and make the length of wiring as short as possible to prevent a leakage current from be- ing generated. (2) comparator the comparator compares the voltage of the composite video signal with the voltage (reference voltage) generated in the refer- ence voltage generating circuit, and converts the composite video signal into a digital value. fig. 8.10.10 clock run-in detect register 8.10.8 start bit detecting circuit this circuit detects a start bit at the line decided in the data slice line specification circuit. the detection of a start bit is as follows:. ? a sampling clock is generated by dividing the reference clock out- put by the timing signal. ? a clock run-in pulse is detected by the sampling clock. ? after detection of the pulse, a start bit pattern is detected from the comparator output. 8.10.9 clock run-in determination circuit this circuit determinates clock run-in by counting the number of pulses in a window of the composite video signal. the reference clock count value in one pulse cycle is stored in bits 3 to 7 of the clock run-in detect register (address 00e4 16 ). read out these bits after the occurrence of a data slicer interrupt (refer to ?.10.12 interrupt request generating circuit?. figure 8.10.10 shows the structure of the clock run-in detect register. b7 b6 b5 b4 b3 b2 b1 b0 clock run-in detect register (crd) [address 00e4 16 ] r w clock run-in detect register 0 to 2 0 r test bits 3 to 7 number of reference clocks to be counted in one clock run-in pulse period. clock run-in detection bit(crd3 to crd7) 0 r read-only after reset functions nam be
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 58 of 139 rej03b0128-0100z 8.10.10 data clock generating circuit this circuit generates a data clock synchronized with the start bit detected in the start bit detecting circuit. the data clock stores cap- tion data to the 16-bit shift register. when the 16-bit data has been stored and the clock run-in determination circuit determines clock run-in, the caption data latch completion flag is set. this flag is reset at a falling edge of the vertical synchronous signal (v sep ). fig. 8.10.11 data clock position register b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 d a t a c l o c k p o s i t i o n r e g i s t e r ( d p s ) [ a d d r e s s 0 0 e 5 1 6 ] d a t a c l o c k p o s i t i o n r e g i s t e r 01 r w f i x t h i s b i t t o 0 . 1 f i x t h i s b i t t o 1 . 0 r w 10 0 b a f t e r r e s e t f unct i on s n ame r w 3 d ata c l oc k pos i t i on set bits (dps3 to dps7) 1 r w 4 t o 7 0 2 f i x t h i s b i t t o 0 . 0 r w
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 59 of 139 rej03b0128-0100z 8.10.11 16-bit shift register the caption data converted into a digital value by the comparator is stored into the 16-bit shift register in synchronization with the data clock. the contents of the high-order 8 bits of the stored caption data can be obtained by reading out data register 2 (address 00e3 16 ) and data register 4 (address 00cf 16 ). the contents of the low-order 8 bits can be obtained by reading out data register 1 (address 00e2 16 ) and data register 3 (address 00ce 16 ), respectively. these registers are reset to ??at a falling edge of v sep . read out data registers 1 and 2 after the occurrence of a data slicer interrupt (refer to ?.10.12 interrupt request generating circuit?. 8.10.12 interrupt request generating circuit the interrupt requests as shown in table 8.10.3 are generated by combination of the following bits; bits 6 and 7 of the caption position register (address 00e6 16 ). read out the contents of data registers 1 to 4 and the contents of bits 3 to 7 of the clock run-in detect register after the occurrence of a data slicer interrupt request. slice line specification mode cps completion flag 1 (bit 0 of dsc2) completion flag 2 (bit 5 of cps) caption data registers 1, 2 caption data registers 3, 4 line 21 a line specified by bits 4 to 0 of cps line 21 line 21 a line specified by bits 4 to 0 of cps invalid invalid a line specified by bits 4 to 0 of cps 16-bit data of line 21 16-bit data of a line specified by bits 4 to 0 of cps 16-bit data of line 21 16-bit data of line 21 16-bit data of a line specified by bits 4 to 0 of cps invalid invalid 16-bit data of a line specified by bits 4 to 0 of cps contents of caption data latch completion flag contents of 16-bit shift register bit 7 0 0 1 1 bit 6 0 1 0 1 cps: caption position register dsc2: data slicer control register 2 t able 8.10.2 contents of caption data latch completion flag and 16-bit shift register caption position register occurence souces of interrupt request at end of data slice line after slicing line 21 after a line specified by bits 4 to 0 of cps after slicing line 21 after slicing line 21 b7 0 1 b6 0 1 0 1 t able 8.10.3 occurence sources of interrupt request
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 60 of 139 rej03b0128-0100z fig. 8.10.12 sync pulse counter register 8.10.13 synchronous signal counter the synchronous signal counter counts the composite sync signal taken out from a video signal in the data slicer circuit or the vertical synchronous signal v sep as a count source. the count value in a certain time (t time) generated by f(x in )/2 13 or f(x in )/2 13 is stored into the 5-bit latch. accordingly, the latch value changes in the cycle of t time. when the count value exceeds ?f 16 , ?f 16 ?is stored into the latch. fig. 8.10.13 synchronous signal counter block diagram the latch value can be obtained by reading out the sync pulse counter register (address 00e9 16 ). a count source is selected by bit 5 of the sync pulse counter register. the synchronous signal counter is used when bit 0 of pwm mode register 1 (address 0208 16 ) is set to ?. figure 8.10.12 shows the structure of the sync pulse counter and figure 8.10.13 shows the synchronous signal counter block diagram. b7 b6 b5 b4 b3 b2 b1 b0 sync pulse counter register (hc) [address 00e9 16 ] r w sync pulse counter register 0 to 4 0r 0r 6, 7 count value (hc0 to hc4) 5 0rw count source (hc5) 0: h sync signal 1: composite sync signal b after reset functions name nothing is assigned. these bits are write disable bits. when these bits are read out, the values are ?. reset 5-bit counter latch (5 bits) f(x in )/2 13 composite sync signal h sync signal counter sync pulse counter register data bus selection gate : connected to black side when reset. b5
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 61 of 139 rej03b0128-0100z 8.11 osd functions t able 8.11.1 outlines the osd functions. this microcomputer incorporates an osd circuit of 32 characters ? 2 lines. there are also 2 display modes which are selected in block units. the display modes are selected by bits 0 and 1 of block con- trol register i (i = 1 and 2). the features of each mode are described below. t able 8.11.1 features of each display mode number of display characters 32 characters ? 2 lines dot structure 16 ? 26 dots (character display area : 16 ? 20 dots) 16 ? 20 dots kinds of characters 254 kinds kinds of character sizes 1 kinds 8 kinds pre-divide ratio (see note) ? 2 (fixed) ? 2, ? 3 dot size 1t c ? 1/2h 1t c ? 1/2h, 1t c ? 1h, 2t c ? 2h, 3t c ? 3h attribute smooth italic, under line, flash border (black) character font coloring 1 screen : 8 kinds (per character unit) character background coloring 1 screen : 8 kinds (per character unit) osd output r, g, b raster coloring possible (per character unit) function auto solid space function window function display position horizontal: 128 levels, vertical: 512 levels display expansion (multiline display) possible parameter notes 1: the divide ratio of the frequency divider (the pre-divide circuit) is referred as ?re-divide ratio?hereafter. 2: the character size is specified with dot size and pre-divide ratio (refer to 8.11.2 dot size). display mode cc mode (closed caption mode) osd mode (border off) (on-screen display mode)
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 62 of 139 rej03b0128-0100z the osd circuit has an extended display mode. this mode allows multiple lines (3 lines or more) to be displayed on the screen by inter- rupting the display each time one line is displayed and rewriting data in the block for which display has been terminated by software. figure 8.11.1 shows the configuration of an osd character. figure 8.11.2 shows the block diagram of the osd circuit. figure 8.11.3 shows the osd control register. figure 8.11.4 shows block control register i. fig. 8.11.1 configuration of osd character display area 16 dots 26 dots 20 dots underline area ? blank area ? ? : displayed only in ccd mode. blank area ? 20 dots osd mode cc mode 16 dots
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 63 of 139 rej03b0128-0100z fig. 8.11.2 block diagram of osd circuit h sync v sync ram for osd 2 bytes ? 32 characters ? 2 lines data bus rom for osd 16 dots ? 20 dots ? 254 characters shift register 16-bit output circuit r g b osd control circuit out control registers for osd osd bort control register (address 00cb 16 ) osd control register (address 00d0 16 ) horizontal position register (address 00d1 16 ) block control register i (addresses 00d2 16 , 00d3 16 ) vertical position register i (addresses 00d4 16 , 00d5 16 ) window register i (addresses 00d6 16 , 00d7 16 ) i/o polarity control register (address 00d8 16 ) raster color register (address 00d9 16 ) osd control register 2 (address 00db 16 ) data slicer clock standard clock for osd f (osc)
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 64 of 139 rej03b0128-0100z fig. 8.11.3 osd control register b7 b6 b5 b4 b3 b2 b1 b0 osd control register (oc) [address 00d0 16 ] b name functions after reset r w osd control register 0 osd control bit (oc0) (see note 1) 0 : all-blocks display off 1 : all-blocks display on 0 1 a utomatic solid space control bit (oc1) 0 : off 1 : on 0 2 0 : off 1 : on 0 0 4o sd mode clock selection bit (oc4) 0 window control bit (oc2) rw rw rw rw rw 3 0 : data slicer clock 1 : internal oscillating clock f(osc) cc mode clock selection bit (oc3) 0 : data slicer clock 1 : internal oscillating clock f(osc) 7 pre-divide ratio selection bit (oc7) (see note 2) 0rw 0 : divide ratio by the block control register 1 : pre-divide ratios = ? 1 for blocks 1 and 2 5, 6 fix these bits to ?. 0 rw 00 notes 1: even this bit is switched during display, the display screen 2: this bit's priority is higher than bci4 of block control register i setting. remains unchanged until a rising (falling) of the next v sync
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 65 of 139 rej03b0128-0100z fig. 8.11.4 block control register i b7 b6 b5 b4 b3 b2 b1 b0 block control register i (bci) (i=1, 2) [addresses 00d2 16 and 00d3 16 ] block control register i 0, 1 display mode selection bits (bci0, bci1) (see note 1) indeterminate 2, 3 dot size selection bits (bci2, bci3) b4 b3 b2 pre-divide ratio dot size 4 pre-divide ratio selection bit (bci4) 5 7 window top/bottom boundary control bit (bci7) notes 1: tc is osd clock cycle divided in pre-divide circuit. 2: h is h sync . 6 v ertical display start position control bit (bci6) bc16: block 1 bc26: block 1 b1 b0 0 0: display off 0 1: cc mode 1 0: osd mode (border off) 1 1: osd mode (border on) 00 01 10 11 00 01 10 11 0 1 ? 2 ? 3 1tc ? 1/2h 1tc ? 1h 2tc ? 2h 3tc ? 3h 1tc ? 1/2h 1tc ? 1h 2tc ? 2h 3tc ? 3h bc17: window top boundary bc27: window bottom boundary b name functions after reset rw rw indeterminate rw indeterminate rw indeterminate rw indeterminate rw indeterminate rw 0: 2 value output control 1: 3 value output control (notes 3) 3: refer to the corresponding figure 8.11.18. outoutput control bit (bci5)
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 66 of 139 rej03b0128-0100z 8.11.1 display position the display positions of characters are specified in units called ?locks.?there are 2 blocks: blocks 1 and 2. up to 32 characters can be displayed in each block (refer to ?.11.5 memory for osd?. the display position of each block can be set in both horizontal and vertical directions by software. the display start position in the horizontal direction can be selected for all blocks from 128-step display positions in units of 4t osc (t osc = osd oscillation cycle). the display start position in the vertical direction for each block can be selected from 512-step display positions in units of 1 t h (in bi- scan mode: 2 t h ) (t h = h sync cycle). blocks are displayed in conformance with the following rules: ?when the display position of block 1 is overlapped with that of block 2 (figure 8.11.5 (b)), block 1 is displayed in front. ?when another block display position appears while one block is displayed (figure 8.11.5 (c)), the block with a larger set value as the vertical display start position is displayed. fig. 8.11.5 display position (hp) v p 2 b l o c k 1 b l o c k 2 ( a ) e x a m p l e w h e n e a c h b l o c k i s s e p a r a t e d b l o c k 1 ( b ) e x a m p l e w h e n b l o c k 2 o v e r l a p s w i t h b l o c k 1 ( b l o c k 2 i s n o t d i s p l a y e d ) (hp) v p 1 v p 2 ( c ) e x a m p l e w h e n b l o c k 2 o v e r l a p s i n p r o c e s s o f b l o c k 1 b l o c k 1 bl oc k 2 n ote: vp 1 or vp 2 i n di cates t h e vert i ca l di sp l ay start pos i t i on o f di sp l ay bl oc k 1 or 2. vp 1 ( h p ) v p 1 = v p 2
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 67 of 139 rej03b0128-0100z the vertical display start position is determined by counting the hori- zontal sync signal (h sync ). at this time, when v sync and h sync are positive polarity (negative polarity), the count starts at the rising edge (falling edge) of h sync signal after the fixed cycle of the rising edge (falling edge) of v sync signal. so the interval from the rising edge (falling edge) of v sync signal to the rising edge (falling edge) of h sync signal needs enough time (2 machine cycles or more) to avoid jitters. the polarity of h sync and v sync signals can be select with the i/o polarity control register (address 00d8 16 ). fig. 8.11.6 supplement explanation for display position w h e n b i t s 0 a n d 1 o f t h e i / o p o l a r i t y c o n t r o l r e g i s t e r ( a d d r e s s 0 0 d 8 1 6 ) a r e s e t t o 1 ( n e g a t i v e p o l a r i t y ) v s y n c s i g n a l i n p u t v sync c ontrol si gnal in microcom p uter 0.25 to 0.50 [ s] ( at f(x in ) = 8mhz) p e r i o d o f c o u n t i n g h s y n c s i g n a l ( s e e n o t e 2 ) h s y n c s i g n a l i n p u t n o t c o u n t 12345 not es 1 : th e vertical position is determined by counting falling edge of h sync si gnal after rising edge of v sync c ontrol signal in the microcomputer. 2 : do not generate falling edge of h sync si gnal near rising edge of v sync c ontrol signal in microcomputer to avoid jitter. 3 : the pulse width of v sync and h sync needs 8 machine cycles or more. 8 ma chine cycles or more 8 m a c h i n e c y c l e s o r m o r e
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 68 of 139 rej03b0128-0100z fig. 8.11.7 vertical position register i (i = 1 and 2) the vertical display start position for each block can be set in 512 steps (where each step is 1t h (t h : h sync cycle)) as values ?0 16 ?to ?f 16 ?in vertical position register i (i = 1 and 2) (addresses 00d4 16 and 00d5 16 ) and values ??or ??in bit 6 of block control register i (i = 1 and 2) (addresses 00d2 16 and 00d3 16 ). the vertical position register is shown in figure 8.11.7. b7 b6 b5 b4 b3 b2 b1 b0 0 to 7 r w ve r tical position register i ve r tical position register i (vpi) (i = 1 and 2) [addresses 00d4 16 , 00d5 16 ] b name functions after reset rw inderterminate ve r tical display start position control bits (vpi0 to vpi7) (see notes) ve r tical display start position = th ? (bci6 ? 16 2 + n) (n: setting value, th: hsync cycle, bci6: bit 6 of block control register i) notes 1: set values except ?0 16 ? to vpi when bci6 is ?. 2: when os21 of osd control register 2 = ?? t h = 1h sync , and os21 of osd control register 2 = ?? t h = 2h sync . the vertical display start position of both blocks can be switched in each step to 1t h or 2t h by setting values ??or ??in bit 1 of osd control register 2 (address 00db 16 ).
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 69 of 139 rej03b0128-0100z the horizontal display start position is common to all blocks, and can be set in 128 steps (where 1 step is 4t osc , t osc being the osd oscillation cycle) as values ?0 16 ?to ?f 16 ?in bits 0 to 6 of the hori- zontal position register (address 00d1 16 ). the horizontal position reg- ister is shown in figure 8.11.8. fig. 8.11.8 horizontal position register notes 1 : 1t c (t c : osd clock cycle divided in pre-divide circuit) gap occurs between the horizontal display start position set by the horizontal position register and the most left dot of the 1st block. accordingly, when 2 blocks have different pre-divide ratios, their horizontal dis- play start position will not match. 2 : the horizontal start position is based on the osd clock source cycle selected for each block. accordingly, when 2 blocks have different osd clock source cycles, their horizontal display start position will not match. 3 : when setting ?0 16 ?to the horizontal position register, it needs an approximately 62t osc (= t def ) interval from a rising edge (when nega- tive polarity is selected) of h sync signal to the horizontal display start position. fig. 8.11.9 notes on horizontal display start position 4 t o s c ? n 4 t o s c ? n h s y n c 1 t c 1 t c 1t c n o t e 1 n o t e 2 b l o c k 2 ( p r e - d i v i d e r a t i o = 2 , c l o c k s o u r c e = d a t a s l i c e r c l o c k ) b l o c k 3 ( p r e - d i v i d e r a t i o = 3 , c l o c k s o u r c e = d a t a s l i c e r c l o c k ) blo ck 4 (pre-divide ratio = 3, clock source = osc1) t d e f t d e f n : v a l u e o f h o r i z o n t a l p o s i t i o n r e g i s t e r ( d e c i m a l n o t a t i o n ) 1 t c : o s d c l o c k c y c l e d i v i d e d i n p r e - d i v i d e c i r c u i t t o s c : o s d o s c i l l a t i o n c y c l e t d e f : 6 2 t o s c b7 b6 b5 b4 b3 b2 b1 b0 horizontal position register (hp) [address 00d1 16 ] bnam e horizontal position register 7 horizontal display start position control bits (hp0 to hp6) nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is ?. functions after reset r w horizontal display start position 4tosc ? n (n: setting value, tosc: osd oscillation cycle) 0 0 rw r 0 to 6 note: the setting value synchronizes with the v sync .
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 70 of 139 rej03b0128-0100z fig. 8.11.10 block diagram of dot size control circuit 8.11.2 dot size the dot size can be selected in block units. the vertical dot size is determined by dividing h sync in the vertical dot size control circuit. the horizontal dot size is determined by dividing the following clock in the horizontal dot size control circuit : the clock gained by dividing the osd clock source (data slicer clock, f (osc) in the pre-divide circuit. the clock cycle divided in the pre-divide circuit is defined as 1t c . the dot size of each block is specified by bits 2 to 4 of block control register i. refer to figure 8.11.4 for the structure of the block control register. the block diagram of the dot size control circuit is shown in figure fig. 8.11.11 definition of dot sizes 1 dot scanning line of f1(f2 ) scanning line of f2(f1 ) 1/2 h 1h 2h 3h 3t c 2t c 1t c 1t c data slicer clock h sync f (osc) oc3 or oc4 synchronous circuit pre-divide circuit clock cycle = 1t c cycle ? 2 0 cycle ? 3 1 bci4 note: to use data slicer clock, set bit 0 of data slicer control register 1 to 1. horizontal dot size control circuit vertical dot size control circuit osd control circuit 0 1 oc7 8.11.10. the pre-divide ratio is specified by bit 7 of the osd control register (address 00d0 16 ) and bit 4 of block control register i (addresses 00d2 16 and 00d3 16 ) . when bit 7 of the osd control register (address 00d0 16 ) is set to "0," the double or triple pre-divide ratio can be chosen per block unit by bit 4 of block control register i. and then, when it is set to "1", the pre-divide ratio increases 1 time (both blocks 1 and 2). the pre-di- vided dot size can be specified per block unit by bits 2 and 3 of block control register i.
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 71 of 139 rej03b0128-0100z 8.11.3 clock for osd the following 2 types of clocks can be selected for osd display: data slicer clock output from the data slicer (approximately 26 mhz) osd clock f (osc) generated based on the reference clock from pin fscin. the osd clock for each block can be selected by: bits 3 and 4 of the clock source control register (addresses 00d0 16 ). a variety of char- acter sizes can be obtained by combining dot sizes with osd clocks. fig. 8.11.12 block diagram of osd selection circuit data slicer circuit data slicer clock (see note) cc mode block osd mode block note: to use data slicer clock, set bit 0 of data slicer control register 1 to ?. ? ? ? ? oc3 oc4 f(osc) clock control register 1 clock control register 1 (cc1) [address 00cd 16 ] b7 b6 b5 b4 b3 b2 b1 b0 0 0 00000 0 0 0 system clock generating circuit control bit (cc10) 0 : operation 1: stop fix these bits to "0" 1 to 7 name b functions after reset r w r w r w fig. 8.11.13 clock control register 1
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 72 of 139 rej03b0128-0100z 8.11.4 field determination display when displaying a block with vertical dot size of 1/2h, the differ- ences in the synchronizing signal waveform of the interlacing system determine whether the field is odd or even. the dot lines 0 and 1 (refer to figure 8.11.15), corresponding to each field, are displayed alternately. in the following, the field determination standard for the case where both the horizontal sync signal and the vertical sync signal are nega- tive-polarity inputs will be explained. a field determination is deter- mined by detecting the time from a falling edge of the horizontal sync signal until a falling edge of the v sync control signal (refer to figure 8.11.6) in the microcomputer and then comparing this time with the time of the previous field. when the time is longer than the previous time, it is regarded as an even field. when the time is shorter, it is regarded as an odd field the contents of this field can be read out by the field determination flag (bit 6 of the i/o polarity control register at address 00d8 16 ). a dot line is specified by bit 5 of the i/o polarity control register (refer to figure 8.11.15). however, the field determination flag read out from the cpu is fixed to ??for even fields or ??for odd fields, regardless of bit 5. fig. 8.11.14 i/o polarity control register 0 0 : at even field at odd field 1 : at even field at odd field b7 b6 b5 b4 b3 b2 b1 b0 i/o polarity control register (pc) [address 00d8 16 ] b name functions after reset r w i/o polarity control register 0h sync input polarity switch bit (pc0) 0 : positive polarity input 1 : negative polarity input 0 1 0 : positive polarity input 1 : negative polarity input 0 2 r, g, b output polarity switch bit (pc2) 0 : positive polarity output 1 : negative polarity output 0 3 out1 output polarity switch bit (pc3) 0 : positive polarity output 1 : negative polarity output 0 5 display dot line selection bit (pc5) (see note) 0 6 field determination flag (pc6) 0 : even field 1 : odd field 1 4, 7 0 v sync input polarity switch bit (pc1) rw rw rw rw rw r rw fix these bits to 0. note: refer to the corresponding figure. 8.11.15 0
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 73 of 139 rej03b0128-0100z fig. 8.11.15 relation between field determination flag and display font field even odd field determination flag(note) display dot line selection bit display dot line 0 (t2 > t1) 1 (t3 < t2) 0 1 0 1 when using the field determination flag, be sure to set bit 0 of the pwm mode register 1 (address 0208 both h sync cignal and v sync signal are negative-polarity input 16 ) to ?. t2 t3 osd rom font configuration diagram dot li n e 0 dot li n e 1 odd dot li n e 0 dot li n e 1 (n 1) field (odd-numbered) t1 0.25 to 0.50[ s] at f(x in ) = 8 mhz cc mode 13579111315 1 3 5 7 9 11 13 15 17 19 21 23 25 26 24 22 20 18 16 14 12 10 8 6 4 2 24 6810 12 14 16 1 3 5 7 9 11 13 15 17 19 20 18 16 14 12 10 8 6 4 2 13579111315 24 6810 12 14 16 osd mode h sync v sync and v sync control signal in microcom- puter upper : v sync signal lower : v sync control signal in micro- computer (n) field (even-numbered) (n + 1) field (odd-numbered) ?, f ont i s di s pl a y e d at even fi e ld , t h e i/ o polarity control re g ister can be read as the fi e ld d eterm i nat i on fl a g : ??is read at odd field, 0 is r ead at e v e n field . note : the field determination flag changes at a rising edge of the v sync control signal (negative-polarity input) in the microcomputer.
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 74 of 139 rej03b0128-0100z 8.11.5 memory for osd there are 2 types of memory for osd: osd rom used to store character dot data and osd ram used to specify the characters and colors to be displayed. osd rom : addresses 11400 16 to 13bff 16 osd ram : addresses 0800 16 to 087f 16 fig. 8.11.16 character font data storing address osd rom address of character font data ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 line number character code f ont bit = ?a 16 ? to ?d 16 = ?0 16 ? to ?f 16 ? (?f 16 ? and ?0 16 ? cannot be used) =0 : left area 1 : right area osd rom address bit line number/character code/font bit 0 line number character code f ont bit 0a 0000 16 7ff0 16 7ff8 16 601c 16 600c 16 600c 16 600c 16 600c 16 11 0b 0c 0d 0e 0f 10 12 601c 16 7ff8 16 7ff0 16 6300 16 6380 16 61c0 16 60e0 16 6070 16 19 13 14 15 16 17 18 6038 16 601c 16 600c 16 0000 16 1d 1a 1b 1c b 0 b7 b 0 b7 line n umber left area right area data in osd rom character font 0 ad16 1 (1) osd rom the dot pattern data for osd characters is stored in the osd rom. to specify the kinds of character font, it is necessary to write the character code into the osd ram. data of the character font is specified as shown in figure 8.11.16.
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 75 of 139 rej03b0128-0100z notes 1 : the 80-byte addresses corresponding to the character code ?f 16 and ?0 16 ?in the osd rom are the test data storing area. set data to the area as follows. addresses 11000 16 + (4 + 2n) ? 100 16 + fe 16 to 1 1000 16 + (5 + 2n) ? 100 16 + 01 16 (n = 0 to 19) (1)mask version (m37150m6/m8/ma/mc/mf-xxxfp) set ?f 16 ?to the area (this sample has test data in this area but the actual product will have different data. when using our font editor, the test data is written automatically. (2)eprom version (M37150EFFP) set the test data to the area. when using our font editor, the test data is written automatically. 1 1500 16 (90 16 ), 11501 16 (a1 16 ) 1 1700 16 (00 16 ), 11701 16 (a2 16 ) 1 1900 16 (48 16 ), 11901 16 (a3 16 ) 1 1b00 16 (00 16 ), 11b01 16 (a4 16 ) 1 1d00 16 (24 16 ), 11d01 16 (a5 16 ) 1 1f00 16 (00 16 ), 11f01 16 (a6 16 ) 12100 16 (12 16 ), 12101 16 (a7 16 ) 12300 16 (00 16 ), 12301 16 (a8 16 ) 12500 16 (09 16 ), 12501 16 (a9 16 ) 12700 16 (00 16 ), 12701 16 (aa 16 ) 12900 16 (81 16 ), 12901 16 (ab 16 ) 12b00 16 (18 16 ), 12b01 16 (ac 16 ) 12d00 16 (00 16 ), 12d01 16 (ad 16 ) 12f00 16 (42 16 ), 12f01 16 (ae 16 ) 13100 16 (24 16 ), 13101 16 (af 16 ) 13300 16 (00 16 ), 13301 16 (b0 16 ) 13500 16 (81 16 ), 13501 16 (b1 16 ) 13700 16 (0c 16 ), 13701 16 (b2 16 ) 13900 16 (06 16 ), 13901 16 (b3 16 ) 13b00 16 (00 16 ), 13b01 16 (b4 16 ) 2 : the character code ?9 16 ?is used for ?ransparent space?when displaying closed caption. therefore, set ?0 16 ?to the 40-byte addresses corresponding to the character code ?9 16 . addresses 11000 16 + (4 + 2n) ? 100 16 + 12 16 to 1 1000 16 + (4 + 2n) ? 100 16 + 13 16 (n = 0 to 19) addresses 11412 16 and 11413 16 addresses 11612 16 and 11613 16 addresses 13812 16 and 13813 16 addresses 13a12 16 and 13a13 16 1 14fe 16 (09 16 ), 114ff 16 (51 16 ) 1 16fe 16 (00 16 ), 116ff 16 (52 16 ) 1 18fe 16 (12 16 ), 118ff 16 (53 16 ) 1 1afe 16 (00 16 ), 11aff 16 (54 16 ) 1 1cfe 16 (24 16 ), 11cff 16 (55 16 ) 1 1efe 16 (00 16 ), 11eff 16 (56 16 ) 120fe 16 (88 16 ), 120ff 16 (57 16 ) 122fe 16 (00 16 ), 122ff 16 (58 16 ) 124fe 16 (90 16 ), 124ff 16 (59 16 ) 126fe 16 (48 16 ), 126ff 16 (5a 16 ) 128fe 16 (24 16 ), 128ff 16 (5b 16 ) 12afe 16 (00 16 ), 12aff 16 (5c 16 ) 12cfe 16 (24 16 ), 12cff 16 (5d 16 ) 12efe 16 (48 16 ), 12eff 16 (5e 16 ) 130fe 16 (00 16 ), 130ff 16 (5f 16 ) 132fe 16 (48 16 ), 132ff 16 (50 16 ) 134fe 16 (90 16 ), 134ff 16 (51 16 ) 136fe 16 (00 16 ), 136ff 16 (52 16 ) 138fe 16 (01 16 ), 138ff 16 (53 16 ) 13afe 16 (80 16 ), 13aff 16 (54 16 ) M37150EFFP m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 76 of 139 rej03b0128-0100z t able 8.11.2 contents of osd ram block character code specification color code specification 31st character 3rd character : 30th character 2nd character 32nd character 31st character 3rd character : 30th character 1st character 2nd character 32nd character 081e 16 0802 16 : 081d 16 0801 16 081f 16 085e 16 0842 16 : 085d 16 0840 16 0841 16 085f 16 083e 16 0822 16 : 083d 16 0821 16 083f 16 087e 16 0862 16 : 087d 16 0860 16 0861 16 087f 16 block 1 display position (from left) block 2 1st character 0800 16 0820 16 (2) osd ram the ram for osd is allocated at addresses 0800 16 to 087f 16 , and is divided into a display character code specification part, color code 1 specification part, and color code 2 specification part for each block. t able 8.11.2 shows the contents of the osd ram. for example, to display the first character position (the left edge) in block 1, write the character code in address 0800 16 and write the color code at 0820 16 . the structure of the osd ram is shown in figure 8.11.17.
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 77 of 139 rej03b0128-0100z fig. 8.11.17 bit structure of osd ram bit name control of character color r control of character color g control of character color b out control flash control underline control italic control bit rf0 rf1 rf2 rf3 rf4 rf5 rf6 rf7 ra0 ra1 ra2 ra3 ra4 ra5 ra6 function character code in osd rom 0: color signal output off 1: color signal output on 0: flash off 1: flash on 0: underline off 1: underline on 0: italic off 1: italic on bit name control of character color r control of character color g control of character color b out control control of background color r control of background color g control of background color b cc mode function character code in osd rom 0: color signal output off 1: color signal output on 0: color signal output off 1: color signal output on osd mode notes 1: read value of bits 7 of the color code is ?. 2: for out control, refer to ?.11.8 out signal. 3: ?f 16 ?and ?0 16 ?cannot be used as character code. character code character code (see note 2) (see note 2) r a 6 r a 5 r a 4 r a 3 r a 2 r a 1 r a 0 rf7 r f 6 r f 5 r f 4 r f 3 r f 2 r f 1r f 0 b 0 b 7 b 0 b 7 b l o c k s 1 , 2 c h a r a c t e r c o d e ( s e e n o t e 3 ) c o l o r c o d e 1 ( s e e n o t e 1 )
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 78 of 139 rej03b0128-0100z 8.11.7 character background color the character background color can be displayed in the character display area only in the osd mode. the character background color for each character is specified by the color code. the 7 kinds of color are specified by bits 0 (r), 1 (g), and 2 (b) of the color code. note : the character background color is displayed in the following parts: (character display area)?character font)?border). accordingly, the character background color does not mix with these color signals. 8.11.6 character color the color for each character is displayed by the color code. the 7 kinds of color are specified by bits 0 (r), 1 (g), and 2 (b) of the color code.
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 79 of 139 rej03b0128-0100z 8.11.8 out signal the out signal is used to control the luminance of the video sig- nal. the output waveform of the out signal is controlled by ra3 of the osd ram. the setting values for controlling out and the cor- responding output waveform are shown in figure 8.11.18. fig. 8.11.18 setting value for controlling out and corresponding output waveform display mode a a' 0 1 block control register i c osd c 1 0 1 0 1 0 1 0 out output control bit (b5) out control (ra3 of osd ram) out=font/border 0 1 vcc about 0.6vcc 0v vcc 0v vcc 0v vcc 0v vcc about 0.6vcc 0v vcc 0v vcc 0v vcc 0v out=area out=font/border out=font/border out=area out=font out=font out=font notes 1: font/border.....in the osd mode (border on), out outputs to the area of font and border. in the osd mode (border off), out outputs to only the font area. area.....................out outputs to entire display area of character. font.....................in the cc mode, out outputs to font area. 2: when the automatic solid space function is off in the cc mode, area outputs according to bit 3 of color code. when it is on, the solid space is automatically output by a character code regardless of ra3. 3: the out signal's three-level outputs are useful only during positive polarity output. 4: for three-level out signal outputs, set port p3 direction register (address 00c7 16 ) bit 2 to 1. 5: for three-level out signal outputs, set about 2 k ? resistor between out pin and v ss . output waveform (a-a')
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 80 of 139 rej03b0128-0100z 8.11.9 attribute the attributes (border, flash, underline, italic) are controlled accord- ing to the character font. the attributes to be controlled are different depending on each mode. cc mode ..................... flash, underline, italic (per character unit) osd mode .................. border (per character unit) (1) underline the underline is output at the 23th and 24th dots in the vertical direc- tion only in the cc mode. the underline is controlled by ra5 of the osd ram. the color of the underline is the same color as that of the character font. (2) flash the character font and the underline are flashed only in the cc mode. the flash is controlled by ra4 of osd ram. in the character font part, the character output part is flashed, but the character back- ground part is not flashed. the flash cycle is based on the v sync count. ?v sync cycle ? 48 800 ms (at display on) ?v sync cycle ? 16 267 ms (at display off) (3) italic the italic is made by slanting the font stored in the osd rom to the right only in the cc mode. the italic is controlled by ra6 of osd ram. d isplay examples of the italic and underline are shown in figure 8.11.19, using ?. notes 1: when setting both the italic and the flash, the italic character flashes. 2: the boundary of character color is displayed in italic. however, the boundary of character background color is not affected by the italic (refer to figure 8.11.20). 3: the adjacent character (one side or both sides) to an italic character is displayed in italic even when the character is not specified to be displayed in italic (refer to figure 8.11.20). 4: italics display cannot be used at pre-divided ratio 1 setting .
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 81 of 139 rej03b0128-0100z fig. 8.11.19 example of attribute display (in cc mode) c o l o r c o d e b i t 6 ( r a 6 ) b i t 5 ( r a 5 ) 00 c o l o r c o d e b i t 6 ( r a 6 ) b i t 5 ( r a 5 ) 10 c o l o r c o d e b i t 6 ( r a 6 ) b i t 5 ( r a 5 ) 01 ( a ) o r d i n a r y( b ) u n d e r l i n e ( c ) i t a l i c ( p r e - d i v i d e r a t i o = 2 ) f l a s hf l a s hf l a s h o f fo f f o no n c o l o r c o d e b i t 6 ( r a 6 ) b i t 5 ( r a 5 ) b i t 4 ( r a 4 ) 111 ( d ) u n d e r l i n e a m d i t a l i c a n d f l a s h
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 82 of 139 rej03b0128-0100z fig. 8.11.20 example of italic display 10 0 1 1 0 1 ( r e f e r t o 8 . 1 1 . 9 n o t e s 2 , 3 )(refer to 8.11.9 notes 2, 3) r a 6 o f o s d r a m n o t e s 1 : t h e d o t t e d l i n e i s t h e b o u n d a r y o f c h a r a c t e r c o l o r . 2 : w h e n b i t 1 o f o s d c o n t r o l r e g i s t e r i s 0 . 2 6 t h c h r a c t e r
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 83 of 139 rej03b0128-0100z (4) border the border is output around the character font (all bordered) in the osd mode only. the border on/off is controlled by bit 0 and 1 of block control register i (refer to figure 8.11.4). the out signal is used for border output. the horizontal size (x) of the border is 1t c (osd clock cycle divided in pre-divide circuit) regardless of the character font dot size. the vertical size (y) differs depending on the screen scan mode and the vertical dot size of the character font. notes 1 : the border dot area is the shaded area as shown in figure 8.11.21. 2 : when the border dot overlaps on the next character font, the charac- ter font has priority (refer to figure 8.11.23 a). when the border dot overlaps the next character back ground, the border has priority (refer to figure 8.11.23 b). 3 : the border in vertical out of the character area is not displayed (refer to figure 8.11.23). fig. 8.11.21 example of border display fig. 8.11.22 horizontal and vertical size of border a l l b o r d e r e d 1 6 d o t s 2 0 d o t s o s d m o d e 1 dot width of border 1 d o t w i d t h o f b o r d e r character font area y x 1/2h 1h, 2h, 3h 1h, 2h, 4h, 6h 1/2h 1h 1h vertical dot size of character font border dot size horizontal size (x) scan mode normal scan mode bi-scan mode vertical size (y) 1tc (osd clock cycle divided in pre-divide circuit)
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 84 of 139 rej03b0128-0100z fig. 8.11.23 border priority character boundary b character boundary a character boundary b
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 85 of 139 rej03b0128-0100z 8.11.10 multiline display this microcomputer can ordinarily display 2 lines on the crt screen by displaying 2 blocks at different vertical positions. in addition, it can display up to 16 lines by using osd interrupts. an osd interrupt request occurs at the point at which that display of each block has been completed. in other words, when a scanning line reaches the point of the display position (specified by the vertical position registers) of a certain block, the character display of that block starts, and an interrupt occurs at the point at which the scan- ning line exceeds the block. notes 1: an osd interrupt does not occur at the end of display when the block is not displayed. in other words, if a block is set to display off by the display control bit of the block control register (addresses 00d2 16 , 00d3 16 ), an osd interrupt request does not occur (refer to figure 8.11.24 (a)). 2: when another block display appears while one block is displayed, an osd interrupt request occurs only once at the end of the second block display (refer to figure 8.11.24 (b)). 3: on the screen setting window, an osd interrupt occurs even at the end of the cc mode block (display off) out of window (refer to figure 8.11.24 (c)). fig. 8.11.24 note on occurence of osd interrupt (b) (c) block 1 (on display) block 2 (on display) block 1?(on display) block 2?(on display) block 1 (on display) block 2 (on display) block 1?(off display) block 2?(off display) ?sd interrupt request ?sd interrupt request ?sd interrupt request ?sd interrupt request ?sd interrupt request ?sd interrupt request no ?sd interrupt request block 1 block 2 ?sd interrupt request ?sd interrupt request ?sd interrupt request ?sd interrupt request block 1 block 2 block 1 on display (osd interrupt request occurs at the end of block display) off display (osd interrupt request does not occur at the end of block display) in cc mode window no ?sd interrupt request no ?sd interrupt request (a)
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 86 of 139 rej03b0128-0100z notes : the character code ?9 16 ?is used for ?ransparent space?when dis- playing closed caption. therefore, set ?0 16 ?to the 40-byte addresses corresponding to the character code ?9 16 . addresses 11000 16 + (4 + 2n) ? 100 16 + 12 16 to 1 1000 16 + (4 + 2n) ? 100 16 + 13 16 (n = 0 to 19) addresses 11412 16 and 11413 16 addresses 11612 16 and 11613 16 addresses 13812 16 and 13813 16 addresses 13a12 16 and 13a13 16 8.11.11 automatic solid space function this function automatically generates the solid space (out blank output) of the character area in the cc mode. the solid space is output in the following areas : ?any character area except character code ?9 16 ?character area on the left and right sides of the above character this function is turned on and off by bit 1 of the osd control register (refer to figure 8.11.3). fig. 8.11.25 display screen example of automatic solid space 0 50 90 90 90606 16 16 16 16 16 16 0 609 16 16 ? ? ? ? 0 9 16 0 6 16 w h e n s e t t i n g t h e c h a r a c t e r c o d e 0 5 1 6 a s t h e c h a r a c t e r a , 0 6 1 6 a s t h e c h a r a c t e r b . ( o s d r a m ) (display screen) 1st char acter 2n d char acter n o b l a n k o u t p u t 31st char acter 32n d char acter th e solid space is automatically output on the left side of the 1st character and on the right side of the 32nd character by setting the 1st and 32nd of the character code. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 87 of 139 rej03b0128-0100z 8.11.13 window function this function sets the top and bottom boundaries for display limits on a screen. the window function is valid only in the cc mode. the top boundary is set by the window register 1 and bit 7 of block con- trol register 1. the bottom boundary is set by window register 1 and bit 7 of block control register 2. this function is turned on and off by bit 2 of the osd control register (refer to figure 8.11.3). window registers 1 and 2 are shown in figures 8.11.27 and 8.11.28. fig. 8.11.26 example of window function osd mode window fgh ij cc mode kl mno cc mode pqrst cc mode osd mode bottom boundary of window top boundary of window screen a bcde uvwxy 8.11.12 scan mode the bi-scan mode corresponds to h sync of twice as much frequency as usual. the vertical display position and the vertical dotsize double compared to the normal scan mode. in the scan mode, the vertical dot size is set by bit 0 of osd control register 2 and the vertical display start position by bit 1, indepen- dently. t able 8.11.3 setting of scan mode bit 0 of osd control register 2 item scan mode normal scan bi-scan 01 ve r tical dot size 1t c ? 1/2h 1t c ? 1h 1t c ? 1h 1t c ? 2h 2t c ? 2h 2t c ? 4h 3t c ? 3h 3t c ? 6h bit 1 of osd control register 2 01 ve r ical display start position a value of verical position register ? 1h a value of verical position register ? 2h the setting value per one step of the top and bottom window borders can be switched to either 1th or 2th by setting ??or ??to bit 1 of osd control register 2 (address 02db 16 ).
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 88 of 139 rej03b0128-0100z fig. 8.11.27 window register 1 fig. 8.11.28 window register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 to 7 r w window register 1 window register 1 (wn1) [address 00d6 16 ] b name functions after reset rw inderterminate window top boundary control bits (wn10 to wn17) window top border position = t h ? (bc17 ? 16 2 + n) (n: setting value, t h : h sync cycle, bc17: bit 7 of block control register 1) notes 1: set values except ?0 16 ? to wn1 when bc17 is ?. 2: set values fit for the following condition: wn1 < wn2. 3: when oc21 of osd control register 2 is ?? t h is 1 h sync . and when ?? t h is 2 h sync . b7 b6 b5 b4 b3 b2 b1 b0 0 to 7 r w window register 2 window register 2 (wn2) [address 00d7 16 ] b name functions after reset rw inderterminate window bottom boundary control bits (wn20 to wn27) window bottom border position = t h ? (bc27 ? 16 2 + n) (n: setting value, t h : h sync cycle, bc27: bit 7 of block control register 2) notes 1: set values fit for the following condition: wn1 < wn2. 2: when oc21 of osd control register 2 is ?? t h is 1 h sync . and when ?? t h is 2 h sync .
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 89 of 139 rej03b0128-0100z 8.11.14 osd output pin control the osd output pins r, g, b and out can also function as ports p5 2 ?5 5 . set the corresponding bit of the osd port control register (address 00cb 16 ) to ??to specify these pins as osd output pins, or to ??to specify as the general-purpose port p5. the input polarity of the h sync and v sync , and the output polarity of signals r, g, b, out can be specified with the i/o polarity control register (address 00d8). set bits to ??to specify positive polarity; ??to specify negative polarity (refer to figure 8.11.14). the structure of the osd port control register is shown in figure 8.11.29. fig. 8.11.29 osd port control register 1 b7 b6 b5 b4 b3 b2 b1 b0 osd port control register (pf) [address 00cb 16 ] b name functions after reset r w osd port control register 0 2 0 30 : g signal output 1 : port p5 3 output 0 0 fix these bits to ?. fix this bit to ?. fix this bit to ?. r r w r w r w w 0, 1 port p5 3 output signal selection bit (pf3) 4 0 : r signal output 1 : port p5 4 output 0 r w port p5 4 output signal selection bit (pf4) 0rw 0 : b signal output 1 : port p5 2 output port p5 2 output signal selection bit (pf2) 5 0 : out signal output 1 : port p5 5 output port p5 5 output signal selection bit (pf5) 7 0 0 indeterminate 6 0
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 90 of 139 rej03b0128-0100z 8.11.15 raster coloring function an entire screen (raster) can be colored by setting bits 4 to 0 of the raster color register. since each of the r, g, b, out pins can be switched to raster coloring output, 8 raster colors can be obtained. when the character color/character background color overlaps with the raster color, the color (r, g, b, out), specified for the character color/character background color, takes priority over the raster color. this ensures that character color/character background color is not mixed with the raster color. the raster color register is shown in figure 8.11.30, an example of raster coloring is shown in figure 8.11.31. fig. 8.11.30 raster color register b7 b6 b5 b4 b3 b2 b1 b0 raster color register (rc) [address 00d9 16 ] b name functions after reset r w raster color register 0 raster color r control bit (rc0) 0 : no output 1 : output 0 1 raster color g control bit (rc1) 0 : no output 1 : output 0 2 0 : no output 1 : output 0 0 raster color b control bit (rc2) rw rw rw rw 3 0 : no output 1 : output raster color out control bit (rc3) 7 fix these bits to ?. 0 rw 0r w 00 0 po rt function selection bit (rc7) 0 : x cin , x cout 1 : p2 6 , p2 7 4 to 6
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 91 of 139 rej03b0128-0100z fig. 8.11.31 example of raster coloring h sync a' a out r g b : character color ?ed (r + out) : border color ?lack (out) : background color ?agenta (r + b + out) : raster color ?lue (b + out) signals across a-a'
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 92 of 139 rej03b0128-0100z fig.8.12.1 sequence at detecting software runaway detection 8. 12 software runaway detect function this microcomputer has a function to decode undefined instructions to detect a software runaway. when an undefined op-code is input to the cpu as an instruction code during operation, the following processing is done. ? the cpu generates an undefined instruction decoding signal. ? the device is internally reset due to the undefined instruction de- coding signal. ? as a result of internal reset, the same reset processing as in the case of ordinary reset operation is done, and the program restarts from the reset vector. note, however, that the software runaway detecting function cannot be disabled. a d h , a d l 0 1 , s 2 0 1 , s 1 p c h p c l p sa d h a d l p c ? ? : u n d e f i n e d i n s t r u c t i o n d e c o d e ? u n d e f i n e d i n s t r u c t i o n d e c o d i n g s i g n a l o c c u r s . i n t e r n a l r e s e t s i g n a l o c c u r s . s y n c a d d r e s s d a t a r e s e t s e q u e n c e 0 1 , sf f f e 1 6 f f f f 1 6 : i n v a l i d : p r o g r a m c o u n t e r s : s t a c k p o i n t e r p c a d l , a d h : j u m p d e s t i n a t i o n a d d r e s s o f r e s e t
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 93 of 139 rej03b0128-0100z 8.13. reset circuit when the oscillation of a quartz-crystal oscillator or a ceramic reso- nator is stable and the power source voltage is 5 v ?10 %, hold the reset pin at low for 2 s or more, then return to high. then, as shown in figure 8.13.2, reset is released and the program starts from the address formed by using the content of address ffff 16 as the high-order address and the content of the address fffe 16 as the low-order address. the internal states of the microcomputer at reset are shown in figures 8.2.2 to 8.2.5. an example of the reset circuit is shown in figure 8.13.1. the reset input voltage must be kept 0.9 v or less until the power source voltage surpasses 4.5 v. fig.8.13.2 reset sequence fig.8.13.1 example of reset circuit power source voltage 0 v reset input voltage 0 v 4.5 v 0.9 v power on vcc reset vss microcomputer 1 5 4 3 0.1 f m51953al x in reset internal reset sync a ddress data 3 2 7 6 8 c o u n t o f x i n c l o c k c y c l e ( s e e n o t e 3 ) re se t address from the vector table ? ? 01, s 01, s-1 01, s-2 fffe ffff a d h , a d l ? ? ? ? ? ad l ad h not es 1 : f(x in ) and f( ) are in the relation : f(x in ) = 2f ( ). 2 : a question mark (?) indicates an undefined state that depends on the previous state. 3 : immediately after a reset, timer 3 and timer 4 are c onnected by hardware. at this time, ?f 16 ?is set in timer 3 and 07 16 ? is set to timer 4. timer 3 counts down with f(x in )/ 16, and reset state is released by the timer 4 overflow signal.
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 94 of 139 rej03b0128-0100z 8.14 clock generating circuit this microcomputer contains two internal oscillator circuits, one os- cillator circuit for the main clock and x cin -x cout for the subclock. the main clock and osd clock are generated based on the refer- ence clock from the fscin pin. the subclock can be obtained by connecting a resonator between x cin and x cout to configure an oscillator circuit. because the resistance-capacitance time constants vary with each resonator, be sure to use the value recommended by the resonator manufacturer. the subclock can also be supplied di- rectly from the fscin pin. for the filt pin used to generate the main clock, insert the filter shown in figure 8.1.4.1. because no re- sistors are included between x cin and x cout , please insert feed- back resistors external to the chip. the osd clock can be chosen to be the data slicer clock (approx. 26 mhz) that is output from the data slicer. after reset, the internal clock f is derived from f(x in ) by dividing it by 2. immediately after power-on, the x in and x cin clocks both start oscil- lating. to select low-speed mode for the internal clock f, set the cpu mode register bit 7 to 1. fig.8.14.1 ceramic resonator circuit example x cin fscin c cin microcomputer x cout r f r d c cout filt external input c1 0.01 f x cin /x cout f(x in ) f( osc ) fscin (3.58mhz) or (4.43mhz) inside system clock of switch circuit f(x cin ) main clock clock for osd sub clock "1" "1" "1" "0" cc2 address 0211 16 bit 2 "0" cm address 00fb 16 bit 7(cm7) "0" oc2 address 00d0 16 bit 3 or 4 data slicer circuit generating circuit system clock 32khz of oscillation circuits f ( ) f(x in ) = 8.95 mhz f(osc) = 26.85 mhz at 3.58 mhz oscillation frequency f(x in ) = 8.86 mhz f(osc) = 26.58 mhz at 4.43 mhz oscillation frequency fig.8.14.2 clock generation circuit
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 95 of 139 rej03b0128-0100z fig.8.14.3 clock frequency setting register fig.8.14.5 clock control register 2 fig.8.14.4 clock control register 1 clock frequency set register(cfs) [address 0210 16 ] clock frequency set register 0 to 7 b7 b6 b5 b4 b3 b2 b1 b0 clock frequency bit (cfs 0 to 7) 0e fscin=3.58mhz fscin=3.58mhz fscin=4.43mhz 0e 8.95 26.85 fscin=4.43mhz 0b 8.86 26.58 main clock frequency f(x in ) [ mhz ] reference clock input setting value set to 0e 16 set to 0b 16 osd clock frequency f( osc ) [ mhz ] name b functions after reset r w r w note: do not set other than the values shown above to cfs. clock control register 1 clock control register 1 (cc1) [address 00cd 16 ] b7 b6 b5 b4 b3 b2 b1 b0 0 0 00000 0 0 0 system clock generating circuit control bit (cc10) 0 : operation 1: stop fix these bits to "0" 1 to 7 name b functions after reset r w r w r w 4 to 7 b7 b6 b5 b4 b3 b2 b1 b0 0 w r 0: fscin input signal 1: x cin -xco ut 0 w r 0 w r 2 00001 0 0 note: this bit is valid when the cpu mode register (address 00fb 16 ) bit 7 (cm7) is set to 1. 3 0 w r fix these bits to "0" fix these bits to "0" fix this bit to "1" clock control register 2 (cc2) [address 0211 16 ] name b functions after reset r w 0,1 clock sauce switch bit (note) (cc22) clock control register 2
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 96 of 139 rej03b0128-0100z 8.14.1 oscillation control (1) stop mode the built-in clock generating circuit is shown in figure 8.14.2. when the stp instruction is executed, the internal clock stops at high. at the same time, timers 3 and 4 are connected by hardware and ?f 16 ?is set in timer 3 and ?7 16 ?is set in timer 4. select f(x in )/16 or f(x cin )/16 as the timer 3 count source (set both bit 0 of timer mode register 2 and bit 6 at address 00c7 16 to ??before the execution of the stp instruction). moreover, set the timer 3 and timer 4 interrupt enable bits to disabled (?? before execution of the stp instruction. the oscillator restarts when an external interrupt is accepted. how- ever, the internal clock keeps its high level until timer 4 overflows, allowing time for oscillation stabilization when a quartz-crystal oscil- lator is used. by settimg bit 7 of timer return setting register (address 00cc 16 ) to ?, ?an arbitrarary value can be set to timer 3 and timer 4. bit 7 of clock control register 3 (address 0212 16 ) can switch port p 10 pin and the clk cont . when clk cont pin is selected, ??is output normally. when an extenal interrupt is recieved in the stp state, the clk cont pin goes back to ??output. (2) wait mode when the wit instruction is executed, the internal clock stops in the high level but the oscillator continues running. this wait state is released at reset or when an interrupt is accepted (see note). since the oscillator does not stop, the next instruction can be executed immediately. note: in the wait mode, the following interrupts are invalid. ?v sync interrupt ?osd interrupt ?all timer interrupts using external clock input from port pin as count source ?all timer interrupts using f(x in )/2 or f(x cin )/2 as count source ?all timer interrupts using f(x in )/4096 or f(x cin )/4096 as count source ?f(x in )/4096 interrupt ?multi-master i 2 c-bus interface interrupt ?data slicer interrupt ?a-d conversion interrupt (3) low-speed mode if the internal clock is generated from the sub-clock (x cin ), a low power consumption operation can be realized by stopping only the main clock x in . to stop the main clock, set bit 6 (cm6) of the cpu mode register (00fb 16 ) to ?.?when the main clock x in is restarted, the program must allow enough time for oscillation to stabilize. note that in the low-power-consumption mode the x cin -x cout drivability can be reduced, allowing even lower power consumption. to reduce the x cin -x cout drivability, clear bit 5 (cm5) of the cpu mode register (00fb 16 ) to ?.?at reset, this bit is set to ??and strong drivability is selected to help the oscillation to start. when executing an stp instruction, set this bit to ??by software before initiating the instruction. fig.8.14.6 clock control register 3 5 0 to 4 r,g,b,out output amplitude level selection bit (cc35) b7 b6 b5 b4 b3 b2 b1 b0 0 w r 0 w r 6 0 w r 7 (cc37) 0: clock control signal 1: p1 0 i/o 0 w r 0 0 0 0 0 0 fix these bits to "0" fix this bit to "0" clock control register 3 (cc3) [address 0212 16 ] name b functions after reset r w clock control register 3 0: 0v? cc 1: 0v?bout 0.6v cc p1 0 function-selection bit (note) note: when used as the clock control signal, set the port 1 direction register (address 00c3 16 ) bit 0 to 1.
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 97 of 139 rej03b0128-0100z fig.8.14.7 clock generating circuit block diagram x cin x cout osc1 clock selection bits (see notes 1, 4) internal system clock selection bit (see notes 1, 3) internal system clock selection bit (see notes 1, 3) main clock (x in ? out ) stop bit (see notes 1, 3) r s q stp instruction wit instruction r s q reset interrupt disable flag i interrupt request r s q reset stp instruction timing (internal clock) timer 3 count source selection bit (see notes 1, 2) ? timer 3 count stop bit (see notes 1, 2) timer 4 count stop bit (see notes 1, 2) timer 3 timer 4 1/2 1/8 ? ? ? notes 1 : the value at reset is ?. 2: refer to timer mode register 2. 3: refer to the cpu mode register. 4: refer to the osd control register. fscin system clock generating circuit
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 98 of 139 rej03b0128-0100z fig.8.14.8 state transitions of system clock (1) the above example assumes that the fscin pin has 3.58 mhz applied to it. the indicates the internal clock. fscin=3.58mhz f(x in )=8.95mhz is stopped ( ?? timer operating fscin=3.58mhz f(x in )=8.95mhz f( )=f(x in )/2 fscin=stopped f(x in )=stopped is stopped ( ?? fscin=3.58mhz f(x in )=8.95mhz f(x cin )=3.58mhz f( )=f(x cin )/2 f(x in )=stopped is stopped ( ?? f(x in )=stopped f(x in )=stopped f(x cin )=3.58mhz is stopped ( ?? timer operating cm7=1 cm7=0 cm6=0 cc10=0 cm6=1 cc10=1 1. when reference clock from fscin is used clock control register 2 (address 0211 16 ) bit 2 = "0" cc10 : clock control register 1 (address 00cd 16 ) bit 0 fscin=3.58mhz fscin=3.58mhz f(x cin )=3.58mhz f(x cin )=stopped fscin=stopped f( )=f(x cin )/2 cm7: internal system clock selection bit 0: f(x in ) selected (high-speed mode) 1: x cin -x cout selected or fsc in input (low-speed mode) cpu mode register (address : 00fb 16 ) cm6: main clock f(x in ) stop bit 0: oscillating 1: stopped the program must allow time for 8.95 mhz oscillation to stabilize reset wit instruction interrupt stp instruction external int, timer int, or si/o int external int external int high-speed operation start mode wit instruction interrupt stp instruction
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 99 of 139 rej03b0128-0100z fig.8.14.9 state transitions of system clock (2) fscin=3.58mhz f(x in )=8.95mhz is stopped ( ?? timer operating f(x in )=8.95mhz f( )=f(x in )/2 fscin=stopped is stopped ( ?? fscin=3.58mhz f(x in )=8.95mhz f( )=16mhz f(x in )=stopped is stopped ( ?? f(x in )=stopped f( )=16mhz f(x in )=stopped is stopped ( ?? timer operating cm7=1 cm7=0 cm6=0 cc10=0 cm6=1 cc10=1 2. when using the 32 khz oscillating clock control register 2 (address 0211 16 ) bit 2 = "1" fscin=3.58mhz fscin=stopped f(x in )=stopped 32khz oscillating 32khz stopped the above example assumes that the fscin and x cin pins have 3.58 mhz and 32 khz signals applied, respectively. the indicates the internal clock. cpu mode register (address 00fb 16 ) fscin=3.58mhz fscin=3.58mhz 32khz oscillating 32khz oscillating 32khz oscillating 32khz oscillating 32khz stopped 0: oscillating 1: stopped cm6: main clock f(x in ) stop bit reset wit instruction interrupt stp instruction external int high-speed operation start mode cm7: internal system clock selection bit 0: f(x in ) selected (high-speed mode) 1: x cin -x cout selected or fsc in input (low-speed mode) wit instruction interrupt stp instruction external int, timer int, or si/o int external int the program must allow time for 8.95 mhz oscillation to stabilize
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 100 of 139 rej03b0128-0100z reset vss vcc circuit example 1 reset vss vcc circuit example 2 note : make the level change from ??to ??at the point at which the power source voltage exceeds the specified voltage. 8.16 addressing mode the memory access is reinforced with 17 kinds of addressing modes. refer to series 740 users manual for details. 8.17 machine instructions there are 71 machine instructions. refer to series 740 users manual for details. 9. technical notes ?the divide ratio of the timer is 1/(n+1). even though the bbc and bbs instructions are executed imme- diately after the interrupt request bits are modified (by the pro- gram), those instructions are only valid for the contents before the modification. at least one instruction cycle is needed (such as an nop) between the modification of the interrupt request bits and the execution of the bbc and bbs instructions. after the adc and sbc instructions are executed (in the decimal mode), one instruction cycle (such as an nop) is needed before the sec, clc, or cld instruction is executed. an nop instruction is needed immediately after the execution of a plp instruction. in order to avoid noise and latch-up, connect a bypass capacitor ( 0.1 f) directly between the v cc pin? ss pin and the v cc pin cnv ss pin, using a thick wire. characteristic value, margin of operation, etc. of versions with built-in eprom and built-in mask rom may differ from each other within the limits of the electrical characteristics in terms of manu- facturing process, built-in rom, difference of a layout pattern, etc. carry out and check an examination equivalent to the system evaluation examination carried out on the eprom version when replacing it with the mask rom version. 8.15 auto-clear circuit when a power source is supplied, the auto-clear function will oper- ate by connecting the following circuit to the reset pin. fig.8.15.1 auto-clear circuit example
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 101 of 139 rej03b0128-0100z v cc power source voltage (see note 4) 4.5 5.0 5.5 v v ss power source voltage 0 0 0 v v ih1 high input voltage p0 0 ?0 7 , p1 0 ?1 6 , p2 0 ?2 7 , p3 0 , p3 1 , p5 0 , p5 1 , 0.8v cc v cc v ______ reset v ih2 high input voltage scl1, scl2, scl3, sda1, sda2 , sda3 0.7v cc v cc v (when using i 2 c-bus) v il1 low input voltage p0 0 p0 7 , p1 0 p1 6 , p2 0 p2 7 , p3 0 , p3 1 0 0.4v cc v v il2 low input voltage scl1, scl2, scl3, sda1, sda2, sda3 0 0.3v cc v (when using i 2 c-bus) v il3 low input voltage (see note 6) ______ p5 0 , p5 1 ,reset, tim2, tim3, int1, 0 0.2v cc v int2, int3, s in , s clk i oh high average output current (see note1) p1 0 p1 6 , p2 0 p2 7 , p3 0 , p3 1 , p5 2 p5 51 ma i ol1 high average output current (see note2) p0 0 p0 7 , p1 0 , p1 5 , p1 6 , p2 0 p2 3 , p5 2 p5 5 2ma i ol2 low average output current (see note 2) p1 1 p1 4 , p3 0 , p3 1 6ma i ol3 low average output current (see note 3) p2 4 p2 7 10 ma f(x cin ) oscillation frequency (for sub-clock operation) x cin 29 32 35 khz f hs1 input frequency tim2, tim3, int1, int2, int3 100 khz f hs2 input frequency s clk 1 mhz f hs3 input frequency scl1, scl2 400 khz f hs4 input frequency horizontal sync. signal of video signal 15.262 15.734 16.206 khz v i input amplitude video signal cv in 1.5 2.0 2.5 v f scin oscillation reference frequency 3.58 or mhz 4.43 v(f scin) input amplitude 1.0 vv 10. absolute maximum ratings symbol parametear conditions ratings unit v cc power source voltage v cc ?.3 to 6 v v i input voltage cnv ss ?.3 to 6 v v i input voltage p0 0 ?0 7 , p1 0 ?1 6 , p2 0 ?2 7 , ?.3? cc + 0.3 v ______ p3 0 , p3 1 , p5 0 , p5 1 , reset, cv in v o output voltage p0 6 , p0 7 , p1 0 ?1 6 , p2 0 ?2 7 , ?.3? cc + 0.3 v p3 0 , p3 1 , p5 2 ?5 5 i oh circuit current p1 0 ?1 6 , p2 0 ?2 7 , p3 0 , p3 1 ,0 to 1 (see note 1) ma p5 2 ?5 5 , i ol1 circuit current p0 0 ?0 7 , p1 0 ?1 5 , p1 6 , p2 0 ?2 3 0 to 2 (see note 2) ma p5 2 ?5 5 , i ol2 circuit current p1 1 ?1 4 , p3 0 , p3 1 0 to 6 (see note 2) ma i ol4 circuit current p2 4 ?2 7 0 to 10 (see note 3) ma p d power dissipation 550 mw t opr operating temperature ?0 to 70 ? t stg storage temperature ?0 to 125 ? limits symbol parametear 1 1. recommended operating conditions (t a = ?0 ? to 70 ?, v cc = 5 v ?10 %, unless otherwise noted) unit all voltages are based on v ss . output transistors are cut off. t a = 25 ? min. typ. max.
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 102 of 139 rej03b0128-0100z max. 30 45 200 2 100 10 0.4 3.0 0.4 0.6 1.3 5 5 130 v cc = 5.5v, f(x in ) = 8.95mhz v cc = 5.5v, f(x in ) = 0, f(x cin ) = 32khz, osd off, data slicer off, low-power dissipation mode set (cm5 = ?? cm6 = ?? v cc = 5.5 v, f(xc in ) = 3.58 mhz v cc = 5.5 v, f(x in ) = 0, f(x cin ) = 32 khz, low-power dissipation mode set (cm5 = ?? cm6 = ?? v cc = 5.5v, f(x in ) = 0, f(x cin ) = 0 v cc = 4.5 v i oh = ?.5 ma v cc = 4.5 v i ol = 0.5 ma v cc = 4.5 v i ol = 10.0 ma v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v v i = 5.5 v v cc = 5.5 v v i = 0 v v cc = 4.5 v 12. electric characteristics (v cc = 5 v ?10 %, v ss = 0 v, f(x in ) = 8.95 mhz, t a = ?0 ? to 70 ?, unless otherwise noted) notes 1: the total current that flows out of the ic must be 20 ma or less. 2: the total input current to ic (i ol1 + i ol2 ) must be 30 ma or less. 3: the total average input current for ports p2 4 ?2 7 and av cc ? ss to ic must be 20 ma or less. 4: connect 0.1 f or more capacitor externally between the power source pins v cc ? ss so as to reduce power source noise. also connect 0.1 f or more capacitor externally between the pins v cc ?nv ss . 5: p0 6 , p0 7 , p1 6 , p2 3 , p2 4 , p2 5 have hysteresis when used as interrupt input pins or timer input pins. p1 1 ?1 4 , p3 0 , p3 1 have hysteresis when used as multi- master i 2 c-bus interface ports. p2 0 ?2 2 have hysteresis when used as serial i/o pins. 6: pin names in each parameter are described as below. (1) dedicated pins: dedicated pin names. (2) double-/triple-function ports ?same limits: i/o port name. ?functions other than ports vary from i/o port limits: function pin name. high output voltage p1 0 ?1 6 , p2 0 ?2 7 , p3 0 , p3 1 , p5 2 ?5 5 , low output voltage p0 0 ?0 7 , p1 0 , p1 5 , p1 6 , p2 0 ?2 3 , p5 2 ?5 5 low output voltage p2 4 ?p2 7 low output voltage p1 1 ?1 4 , p3 0 , p3 2 hysteresis (see note 6) ____________ reset, p5 0 , p5 1 , int1, int2, int3, tim2, tim3, s in , s clk , scl1, scl2, scl3, sda1, sda2, sda3 high input leak current p0 0 ?0 7 , p1 0 ?1 6 , p2 0 ?2 7 , ____________ p3 0 , p3 1 , reset, p5 0 , p5 1 , high input leak current p0 0 ?0 7 , p1 0 ?1 6 , p2 0 ?2 7 , p3 0 , ____________ p3 1 , p5 0 , p5 1 , reset i 2 c-bus ?bus switch connection resistor (between scl1 and scl2, sda1 and sda2) i cc symbol parametear t est conditions osd off data slicer off osd on data slicer on stop mode w ait mode system operation power source current v oh v ol v t+ v t i izh i izl r bs t est circuit 1 min. 2.4 limits i ol = 3 ma i ol = 6 ma t yp. 15 30 60 1 25 1 0.5 2 3 4 5 4 unit ma a ma a v v v a a ?
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 103 of 139 rej03b0128-0100z a vss vcc fscin icc 3.58 mhz or 4.43 mhz from asic + po we r source voltage vss vc c v v oh or v ol i oh or i ol 4.5 v each output pin after setting each output pin to high level when measuring v oh and to low level when measuring v ol , each pin is measured. vss vcc 5.0 v each input pin vss vcc 5.5 v each input pin 5.5 v or 0 v a i izh or i izl vss vcc v bs 4.5v scl1 or sda1 i bs a r bs = v bs /i bs scl2 or sda2 r bs fig.12.1 measurement circuits 1 3 5 2 4
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 104 of 139 rej03b0128-0100z 13. a-d converter characteristics (v cc = 5 v ?10 %, v ss = 0 v, f(x in ) = 8.95 mhz, t a = ?0 ? to 70 ?, unless otherwise noted) resolution non-linearity error differencial non-linearity error zero transition error full-scale transition error max. 7 ?.5 ?.9 2 ? bits lsb lsb lsb lsb min. limits unit t est conditions parameter symbol v 0t v fst i ol (sum) = 0 ma t yp. 14. multi-master i 2 c-bus bus line characteristics bus free time hold time for start condition low period of scl clock rising time of both scl and sda signals data hold time high period of scl clock falling time of both scl and sda signals data set-up time set-up time for repeated start condition set-up time for stop condition t buf t hd; sta t low t r t hd; dat t high t f t su; dat t su; sta t su; sto max. 1000 300 min. 1.3 0.6 1.3 20+0.1c b 0 0.6 20+0.1c b 100 0.6 0.6 max. 300 0.9 300 s s s ns s s ns ns s s unit standard clock mode high-speed clock mode parameter symbol note: c b = total capacitance of 1 bus line fig.14.1 definition diagram of timing on multi-master i 2 c-bus min. 4.7 4.0 4.7 0 4.0 250 4.7 4.0 s d a scl p t b u f s t hd ; sta t l o w t r t hd ; dat t h igh t f t su ; dat t su ; sta sr p t su ; sto t hd ; sta s sr p : start condition : restart condition : stop condition
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 105 of 139 rej03b0128-0100z 15. prom programming method the built-in prom of the one time prom version (blank) and the built-in eprom version can be read or programmed with a general- purpose prom programmer using a special programming adapter. the prom of the one time prom version (blank) is not tested or screened in the assembly process nor any following processes. to ensure proper operation after programming, the procedure shown in figure 15.1 is recommended to verify programming. fig. 15.1 programming and testing of one time prom version programming with prom programmer screening (caution) (150? for 40 hours) verification with prom programmer functional check in target device caution : the screening temperature is far higher than the storage temperature. never expose to 150? exceeding 100 hours. name of programming adapter pca7450fp product M37150EFFP
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 106 of 139 rej03b0128-0100z 16. data required for mask orders the following are necessary when ordering a mask rom product: ?mask rom order confirmation form ?mark specification form ?data to be written to rom, in eprom form (three identical copies) or fdk when using eprom: three sets of 32-pin dip type 27c101
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 107 of 139 rej03b0128-0100z 17. one time prom version M37150EFFP marking M37150EFFP xxxxxxx xxxxxxx is lot number
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 108 of 139 rej03b0128-0100z 18. appendix pin configuration (top view) 1 16 1 1 1 2 13 14 15 5 6 7 8 9 1 0 2 3 4 1 7 18 19 20 2 1 4 2 27 3 2 3 1 30 29 28 3 8 3 7 3 6 3 5 3 4 3 3 4 1 4 0 3 9 2 6 25 24 23 2 2 p1 1 /scl1 p0 0 /pwm0 p0 1 /pwm1 p0 2 /pwm2 p0 3 /pwm3/ad1 p0 4 /pwm4/ad2 p0 5 /ad3 p0 6 /int2/ad4 p0 7 /int1 p2 0 /sclk/ad5 p2 1 /sout/ad6 p2 2 /sin/ad7 p2 3 /tim3 p2 4 /tim2 p2 5 /int3 p2 6 /x cin p2 7 /x cout cnv ss v ss p1 2 /scl2 p1 3 /sda1 p1 4 /sda2 p1 6 /ad8/tim2 p5 0 /h sync p5 1 /v sync p5 2 /b p5 3 /g p5 4 /r p5 5 /out clk cont /p1 0 p3 0 /sda3 p3 1 /scl3 p1 5 fscin reset cvin v hold v cc hlf filt m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP nc outline 42p2r * open 20-pin.
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 109 of 139 rej03b0128-0100z memory map 0000 16 00c0 16 00ff 16 sfr1 area not used ffff 16 ffde 16 ff00 16 interrupt vector area special page 087f 16 0800 16 osd ram (128 bytes) zero page 0200 16 020f 16 sfr2 area not used 0300 16 00bf 16 0100 16 01ff 16 05bf 16 053f 16 not used 0b3f 16 0900 16 1000 16 not used ro m correction function v ector 1: address 0300 16 v ector 2: address 0320 16 0320 16 06ff 16 6000 16 8000 16 a000 16 4000 16 m37150mf-xxxfp, M37150EFFP rom (60k bytes) m37150mc-xxxfp rom (48k bytes) m37150ma-xxxfp rom (40k bytes) m37150m8-xxxfp rom (32k bytes) 10000 16 1ffff 16 not used m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP m37150m6-xxxfp rom (24k bytes) 13bff 16 11400 16 osd rom (10k bytes) not used m37150mf-xxxfp, M37150EFFP ram (2048 bytes) m37150mb-xxxfp ram (1152 bytes) m37150ma/mc- xxxfp ram (1472 bytes) m37150m6- xxxfp ram (1024 bytes)
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 110 of 139 rej03b0128-0100z memory map of special function register (sfr) b 7b0 b 7 b 0 d0 16 d1 16 d2 16 d3 16 d4 16 d5 16 d6 16 d7 16 d8 16 d9 16 da 16 db 16 dc 16 dd 16 de 16 df 16 c0 16 c1 16 c2 16 c3 16 c4 16 c5 16 c6 16 c7 16 c8 16 c9 16 cb 16 cc 16 cd 16 ce 16 cf 16 ca 16 port p5(p5) caption data register 3 (cd3) caption data register 4 (cd4) osd control register (oc) port p1(p1) port p1 direction register (d1) port p3(p3) port p3 direction register (d3) port p2(p2) port p2 direction register (d2) port p0(p0) port p0 direction register (d0) horizontal position register (hp) block control register 1(bc1) block control register 2(bc2) ve rtical position register 1(vp1) ve rtical position register 2(vp2) window register 1(wn1) interrupt input polarity control register (re) osd port control register (pf) window register 2(wn2) i/o polarity control register (pc) raster color register (rc) timer return set register (tms) clock control register 1 (cc1) osd control register 2(oc2) sfr1 area (addresses c0 16 to df 16 ) address register bit allocation state immediately after reset : ??immediately after reset : indeterminate immediately after reset 0 1 ? : ??immediately after reset : fix this bit to ?? (do not write ?? : function bit : no function bit : fix this bit to ?? (do not write ?? name : 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 16 00 16 00 16 00 16 00 16 00 16 00 16 ? ? ? ? 40 16 00 16 ? ? ? 00 16 00 16 ? ? 00 16 00 16 0 0 0 0 0 0 ? ? 00 16 00 16 ? 00 16 ? 0 0 1 0 0 0 0 1 ? ? 0 ? ? ? ? ? bsel21 bsel20 p31 p30 outs p31d p30d t3sc pf3 pf2 pf5 pf4 cc10 cdl27 cdl26 cdl25 cdl24 cdl23 cdl22 cdl21 cdl20 cdh27 cdh26 cdh25 cdh24 cdh23 cdh22 cdh21 cdh20 oc3 oc2 oc4 oc1 oc0 hp3 hp2 hp4 hp1 hp0 hp5 hp6 bc13 bc12 bc14 bc11 bc10 bc16 bc17 bc23 bc22 bc24 bc21 bc20 bc26 bc27 vp13 vp12 vp14 vp11 vp10 vp16 vp17 vp15 vp23 vp22 vp24 vp21 vp20 vp26 vp27 vp25 wn13 wn12 wn14 wn11 wn10 wn16 wn17 wn15 wn23 wn22 wn24 wn21 wn20 wn26 wn27 wn25 pc3 pc2 pc1 pc0 pc5 pc6 rc3 rc2 rc1 rc0 rc7 int3 int2 int1 0 1 0 0 0 0 0 tms oc7 bc15 bc25 oc21 oc20 t2sc ? ? ? 0 ? 0 0 0 0 0 0 0 0 0 ? 0 0 0 0
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 111 of 139 rej03b0128-0100z f0 16 f1 16 f2 16 f3 16 f4 16 f5 16 f6 16 f7 16 f8 16 f9 16 fa 16 fb 16 fc 16 fd 16 fe 16 ff 16 e0 16 e1 16 e2 16 e3 16 e4 16 e5 16 e6 16 e7 16 e8 16 e9 16 eb 16 ec 16 ed 16 ee 16 ef 16 ea 16 address serial i/o register (sio) a-d control register 1 (ad1) timer 5 (t5) timer 6 (t6) timer 1 (t1) caption data register 1 (cd1) caption position register (cps) data slicer test register 2 clock run-in detect register (crd) data clock position register (dps) register data slicer control register 1 (dsc1) data slicer control register 2 (dsc2) timer 2 (t2) timer 3 (t3) timer 4 (t4) timer mode register 1 (tm1) timer mode register 2 (tm2) i 2 c data shift register (s0) i 2 c control register (s1d) i 2 c clock control register (s2) interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 1 (icon1) interrupt control register 2 (icon2) data slicer test register 1 synchronous signal counter register (hc) a-d control register 2 (ad2) cpu mode register (cpum) b7 b0 bit allocation state immediately after reset b7 b0 sfr1 area (addresses e0 16 to ff 16 ) caption data register 2 (cd2) serial i/o mode register (sm) i 2 c status register (s1) i 2 c address register (s0d) : ? immediately after reset : indeterminate immediately after reset 0 1 ? : ? immediately after reset : fi x this bit to ? (do not write ?? : function bit : no function bit : fi x this bit to ? (do not write ?? name : 1 0 tm20 tm21 tm22 tm23 tm24 tm10 tm11 tm12 tm13 tm14 cm2 tm1r tm2r tm3r tm4r osdr vscr in3r ck0 in1r dsr s1r tm1e tm2e tm3e tm4e osde vsce in1e dse s1e in2e tm25 00 16 ff 16 07 16 ff 16 07 16 07 16 tm15 tm16 tm17 tm26 tm27 ? sad0 sad1 sad2 sad3 sad4 sad5 sad6 rbw lrb ad0 aas al pin bb trx mst bc0 bc1 bc2 eso als bsel0 bsel1 ccr0 ccr1 ccr2 ccr3 ccr4 ack 00 16 00 16 00 16 ckr in2r iicr tm56r in3e cke iice tm56e tm56c 0 0 cm7 cm5 cm6 sm0 sm1 sm2 sm3 adc10 adc11 adc12 adc14 adc20 adc21 adc22 adc25 adc26 sm5 sm6 adc24 adc23 10bit sad f ast mode ? 00 16 00 16 00 16 ff 16 dsc10 dsc11 dsc12 dsc20 dsc23 dsc24 dsc25 crd3 crd4 crd5 crd6 crd7 dps3 dps4 dps5 dps6 dps7 cps0 cps3 cps4 cps5 cps1 cps2 cps6 cps7 hc0 hc3 hc4 hc5 hc1 hc2 0? 0? 0 ? ?? 00 0 ? 01100 01 1 0 0 00 1 0 1 00 0 0 00 16 cdh10 cdh13 cdh14 cdh15 cdh11 cdh12 cdh16 cdh17 cdl10 cdl13 cdl14 cdl15 cdl11 cdl12 cdl16 cdl17 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 d1 d2 d3 d4 d5 d6 d7 d0 0 0 00?00 0 0 0 0 01 0 0? ack bit 09 16 3c 16
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 112 of 139 rej03b0128-0100z sfr2 area (addresses 200 16 to 20f 16 ) b7 b0 b7 b0 200 16 201 16 202 16 203 16 204 16 206 16 205 16 207 16 208 16 209 16 20b 16 20c 16 20d 16 20e 16 20a 16 20f 16 210 16 211 16 212 16 pwm2 register (pwm2) pwm4 register (pwm4) pwm0 register (pwm0) pwm1 register (pwm1) pwm3 register (pwm3) clock frequency set register ( cfs ) pwm mode register 2 (pm2) rom correction address 1 (low-order) rom correction enable register (rcr) pwm mode register 1 (pm1) rom correction address 2 (high-order) rom correction address 1 (high-order) rom correction address 2 (low-order) clock control register 2(cc2) clock control register 3(cc3) : 0 immediately after reset : indeterminate immediately after reset 0 1 ? : 1 immediately after reset : fix this bit to 0 (do not write 1 ) : function bit : no function bit : fix this bit to 1 (do not write 0 ) name : 1 0 address register bit allocation state immediately after reset 0 0 0 00 16 00 16 00 16 00 16 00 16 0 0 0 0 1 1 1 0 ? ? ? ? 0 ? ? 0 00 16 ? pm13 pm10 rc0 cc22 cc35 00 16 pm23 pm20 pm24 pm21 pm22 rc1 0 0 0 0 1 0 0 cc37 00 16 00 16 00 16 ? ? ? ? ? ? ? 0 0 0 0 0 0 ?
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 113 of 139 rej03b0128-0100z b7 b0 b7 b 0 1 r e g i s t e r processor status register (ps) b i t a l l o c a t i o ns t a t e i m m e d i a t e l y a f t e r r e s e t program counter (pc h ) program counter (pc l ) contents of address ffff 16 c ontents of address fffe 16 i z c d b t v n?? ? ? ? ? ? : fix to this bit to ?? ( do not write to 1) : < bit allocation > < s t a t e i m m e d i a t e l y a f t e r r e s e t > f unction bit : n o f u n c t i o n b i t : fix to this bit to ?? ( do not write to 0) n a m e : : 0 i m m e d i a t e l y a f t e r r e s e t : i ndeterminate immediately after reset 0 1 ? : 1 i m m e d i a t e l y a f t e r r e s e t 1 0
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 114 of 139 rej03b0128-0100z structure of register the figure of each register structure describes its functions, contents at reset, and attributes as follows: v a l u e s i m m e d i a t e l y a f t e r r e s e t r e l e a s e b i t a t t r i b u t e s ( n o t e 1 ) ( n o t e 2 ) b i t p o s i t i o n 2 : b i t a t t r i b u t e s t h e a t t r i b u t e s o f c o n t r o l r e g i s t e r b i t s a r e c l a s s i f i e d i n t o 3 t y p e s : r e a d - o n l y , w r i t e - o n l y a n d r e a d a n d w r i t e . i n t h e f i g u r e , t h e s e a t t r i b u t e s a r e r e p r e s e n t e d a s f o l l o w s : : b i t i n w h i c h n o t h i n g i s a s s i g n e d n o t e s 1 : v a l u e s i m m e d i a t e l y a f t e r r e s e t r e l e a s e 0 0 a f t e r r e s e t r e l e a s e 1 1 a f t e r r e s e t r e l e a s e i n d e t e r m i n a t e i n d e t e r m i n a t e a f t e r r e s e t r e l e a s e r e a d e n a b l e d r e a d d i s a b l e d r r r e a d w r i t e e n a b l e d w r i t e d i s a b l e d 0 c a n b e s e t b y s o f t w a r e , b u t 1 c a n n o t b e s e t . w w r i t e w ? b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b a f t e r r e rw c p u m o d e r e g i s t e r 0 , 1 2 3 , 4 0 1 n a m ef u n c t i o n s p r o c e s s o r m o d e b i t s ( c m 0 , c m 1 ) 0 0 : s i n g l e - c h i p m o d e 0 1 : 1 0 : n o t a v a i l a b l e 1 1 : f i x t h e s e b i t s t o 1 . 1 s t a c k p a g e s e l e c t i o n b i t ( s e e n o t e ) ( c m 2 ) 1 b 1 b 0 0 : 0 p a g e 1 : 1 p a g e 1 0 0 5 1 n o t h i n g i s a s s i g n e d . t h i s b i t i s w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 1 . 6 , 7 0 c l o c k s w i t c h b i t s ( c m 6 , c m 7 ) 0 0 : f ( x i n ) = 8 m h z 0 1 : f ( x i n ) = 1 2 m h z 1 0 : f ( x i n ) = 1 6 m h z 1 1 : d o n o t s e t b 7 b 6 c p u m o d e r e g i s t e r ( c p u m ) ( c m ) [ a d d r e s s 0 0 f b 1 6 ] r w rw rw r w rw < e x a m p l e >
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 115 of 139 rej03b0128-0100z address 00c1 16 , 00c5 16 address 00c2 16 b7 b6 b5 b4 b3 b2 b1 b0 port pi direction register (di) (i=0, 2) [addresses 00c1 16, 00c5 16 ] bn ame functions after reset r w port pi direction register 1 : port pi 0 output mode 0 : port pi 0 input mode 0 1 0 0 : port pi 1 input mode 1 : port pi 1 output mode 0 2 3 4 5 6 0 : port pi 2 input mode 1 : port pi 2 output mode 0 0 : port pi 3 input mode 1 : port pi 3 output mode 0 0 : port pi 4 input mode 1 : port pi 4 output mode 0 0 : port pi 5 input mode 1 : port pi 5 output mode 0 0 : port pi 6 input mode 1 : port pi 6 output mode 0 7 0 : port pi 7 input mode 1 : port pi 7 output mode 0 port pi direction register rw rw rw rw rw rw rw rw 0 1 2 port p1 register w r 4 b7 b6 b5 b4 b3 b2 b1 b 0 fix this bit to "0" 0 w r w r 5 6 7 3 w r w r w r w r w r 0 port p1 register port p1 register (p1) [address 00c2 16 ] b name functions after reset r w port p1 0 data port p1 1 data port p1 2 data port p1 3 data port p1 4 data port p1 5 data port p1 6 data indeterminate indeterminate indeterminate indeterminate indeterminate indeterminate indeterminate
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 116 of 139 rej03b0128-0100z address 00c3 16 address 00c6 16 1 0 2 po rt p1 direction register 4 b7 b6 b5 b4 b3 b2 b1 b0 fix this bit to "0" 1 w r 0 w r 5 6 7 3 0 w r 0 w r 0 w r 0 w r 1 w r 0 w r note: when using p10 as a general-purpose port, set the clock control register 3 (address 0212 16 ) bit 7 to 1. when using p10 as a clock control signal, refer to 8.14.1 oscillation control. p10 becomes clock control signal output and ?h? output setting immediately after reset release , and p16 becomes ?l? output setting after reset release. 0 po rt p1 direction register po rt p1 direction register ( d1) [address 00 c3 16 ] b name functions after reset r w 0 : port p1 0 input mode (note) 1 : port p1 0 output mode 0 : port p1 1 input mode 1 : port p1 1 output mode 0 : port p1 2 input mode 1 : port p1 2 output mode 0 : port p1 3 input mode 1 : port p1 3 output mode 0 : port p1 4 input mode 1 : port p1 4 output mode 0 : port p1 5 input mode 1 : port p1 5 output mode 0 : port p1 6 input mode 1 : port p1 6 output mode port p3 register (p3) [address 00c6 16 ] port p3 register 0 1 2 port p3 register indeterminate indeterminate w r 4 to 7 b7 b6 b5 b4 b3 b2 b1 b0 nothing is assigned. this bit is write disable bit. when this bit is read out, the value is "0." w r 0 w r 0 ? r 3 (bsel20 ) (see note) 0 w r scl3/p3 1 -scl1/p1 1 sda3/p3 0 -sda1/p1 3 connection control bit (bsel21) notes for the ports used as the multi-master i 2 c-bus interface, set their direction registers to 1. to use scl3 and sda3, set the i 2 c control register (address 00f9 16 ) bits 6?7 to 0. bname f unctions after reset r w port p3 0 data port p3 1 data switch bit of i 2 c-bus interface and port p3 0 : port p3 0 , port p3 1 1 : i 2 cbus (sda3,scl3) 0 : cutting 1 : connection
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 117 of 139 rej03b0128-0100z address 00c7 16 0 1 2 po rt p3 direction register (see note 1) 0 w r b7 b6 b5 b4 b3 b2 b1 b 0 0 w r 0 w r 0 w r 3 output amplitude level selection bit (outs) (see note 2) 0 : 2 value output 1 : 3 value output fix this bit to "0." 4 , 5 nothing is assigned fix these bits when this bit are read out, the value are "0." 0 ? r 6 7 timer 3 (t3sc) refer to explanation of a timer 0 : p2 4 input 1 : p1 6 input timer 2 0 w r 0 w r 0 notes 1 : when using the port as the i 2 c-bus interface, set the port p3 direction register to 1. 2 : use the clock control register 3 (address 0212 16 ) bit 5 to select the binary output level of out. (t2sc) po rt p3 direction register po rt p3 direction register (d3) [address 00c7 16 ] b name functions after reset r w 0 : port p3 0 input 1 : port p3 0 output 0 : port p3 1 input 1 : port p3 1 output address 00ca 16 0, 1 2 3 b7 b6 b5 b4 b3 b2 b1 b0 w r 4 fix these bits to "0 ." 5 indeterminate w ? indeterminate w r w r w r w r w r 0 0 0 0 port p5 register (p5) [address 00ca 16 ] port p5 register port p5 register port p5 2 data port p5 3 data port p5 4 data port p5 5 data indeterminate indeterminate indeterminate indeterminate indeterminate fix these bits to "0." 6 7 b name functions after reset r w
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 118 of 139 rej03b0128-0100z 1 b7 b6 b5 b4 b3 b2 b1 b0 osd port control register (pf) [address 00cb 16 ] b name functions after reset r w osd port control register 0 2 0 30 : g signal output 1 : port p5 3 output 0 0 fix these bits to ?0.? fix this bit to ?1.? fix this bit to ?0.? r ? r w r w r w w 0, 1 port p5 3 output signal selection bit (pf3) 4 0 : r signal output 1 : port p5 4 output 0 r w port p5 4 output signal selection bit (pf4) 0rw 0 : b signal output 1 : port p5 2 output port p5 2 output signal selection bit (pf2) 5 0 : out signal output 1 : port p5 5 output port p5 5 output signal selection bit (pf5) 7 0 0 indeterminate ? 6 0 address 00cb 16 address 00cc 16 timer return setting register timer return setting register (tms) [address 00cc 16 ] b7 b6 b5 b4 b3 b2 b1 b0 0w r fix these bits to "0." fix this bit to "1." fix this bit to "0." 7 0 stop mode return selection bit (tms) 0: timer count "07ff 16 " 1: timer count variable w r 6 0 w r 5 0 w r 0 1 0 0 0 0 0 name b functions after reset r w 0 to 4
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 119 of 139 rej03b0128-0100z address 00cd 16 address 00d0 16 clock control register 1 clock control register 1 (cc1) [address 00cd 16 ] b7 b6 b5 b4 b3 b2 b1 b0 0 0 00000 0 0 0 system clock generating circuit control bit (cc10) 0 : operation 1: stop fix these bits to "0" 1 to 7 name b functions after reset r w r w r w b7 b6 b5 b4 b3 b2 b1 b0 osd control register (oc) [address 00d0 16 ] bnam e functions after reset r w osd control register 0 osd control bit (oc0) (see note 1) 0 : all-blocks display off 1 : all-blocks display on 0 1 a utomatic solid space control bit (oc1) 0 : off 1 : on 0 2 0 : off 1 : on 0 0 4o sd mode clock selection bit (oc4) 0 window control bit (oc2) rw rw rw rw rw 3 0 : data slicer clock 1 : internal oscillating clock f(osc) cc mode clock selection bit (oc3) 0 : data slicer clock 1 : internal oscillating clock f(osc) 7 pre-divide ratio selection bit (oc7) (see note 2) 0rw 0 : divide ratio by the block control register 1 : pre-divide ratios = ? 1 for blocks 1 and 2 5, 6 fix these bits to ?0.? 0 rw 00 notes 1: even this bit is switched during display, the display screen 2: this bit's priority is higher than bci4 of block control register i setting. remains unchanged until a rising (falling) of the next v sync
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 120 of 139 rej03b0128-0100z b7 b6 b5 b4 b3 b2 b1 b0 block control register i (bci) (i=1, 2) [addresses 00d2 16 and 00d3 16 ] block control register i 0, 1 display mode selection bits (bci0, bci1) (see note 1) indeterminate 2, 3 dot size selection bits (bci2, bci3) b4 b3 b2 pre-divide ratio dot size 4 pre-divide ratio selection bit (bci4) 5 7 window top/bottom boundary control bit (bci7) notes 1: tc is osd clock cycle divided in pre-divide circuit. 2: h is h sync . 6 v ertical display start position control bit (bci6) bc16: block 1 bc26: block 1 b1 b0 0 0: display off 0 1: cc mode 1 0: osd mode (border off) 1 1: osd mode (border on) 00 01 10 11 00 01 10 11 0 1 ? 2 ? 3 1tc ? 1/2h 1tc ? 1h 2tc ? 2h 3tc ? 3h 1tc ? 1/2h 1tc ? 1h 2tc ? 2h 3tc ? 3h bc17: window top boundary bc27: window bottom boundary b name functions after reset rw rw indeterminate rw indeterminate rw indeterminate rw indeterminate rw indeterminate rw 0: 2 value output control 1: 3 value output control (notes 3) 3: refer to the corresponding figure 8.11.18. outoutput control bit (bci5) address 00d1 16 address 00d2 16 , 00d3 16 b7 b6 b5 b4 b3 b2 b1 b0 horizontal position register (hp) [address 00d1 16 ] bnam e horizontal position register 7 horizontal display start position control bits (hp0 to hp6) nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is ?0.? functions after reset r w horizontal display start position 4tosc ? n (n: setting value, tosc: osd oscillation cycle) 0 0 rw r? 0 to 6 note: the setting value synchronizes with the v sync .
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 121 of 139 rej03b0128-0100z address 00d4 16 , 00d5 16 address 00d6 16 address 00d7 16 b7 b6 b5 b4 b3 b2 b1 b0 0 to 7 r w ve r tical position register i ve r tical position register i (vpi) (i = 1 and 2) [addresses 00d4 16 , 00d5 16 ] b name functions after reset rw inderterminate ve r tical display start position control bits (vpi0 to vpi7) (see notes) ve r tical display start position = th ? (bci6 ? 16 2 + n) (n: setting value, th: hsync cycle, bci6: bit 6 of block control register i) notes 1: set values except ?00 16 ? to vpi when bci6 is ?0.? 2: when os21 of osd control register 2 = ?0?, t h = 1h sync , and os21 of osd control register 2 = ?1?, t h = 2h sync . b7 b6 b5 b4 b3 b2 b1 b0 0 to 7 r w window register 1 window register 1 (wn1) [address 00d6 16 ] b name functions after reset rw inderterminate window top boundary control bits (wn10 to wn17) window top border position = t h ? (bc17 ? 16 2 + n) (n: setting value, t h : h sync cycle, bc17: bit 7 of block control register 1) notes 1: set values except ?00 16 ? to wn1 when bc17 is ?0.? 2: set values fit for the following condition: wn1 < wn2. 3: when oc21 of osd control register 2 is ?0?, t h is 1 h sync . and when ?1?, t h is 2 h sync . b7 b6 b5 b4 b3 b2 b1 b0 0 to 7 r w window register 2 window register 2 (wn2) [address 00d7 16 ] b name functions after reset rw inderterminate window bottom boundary control bits (wn20 to wn27) window bottom border position = t h ? (bc27 ? 16 2 + n) (n: setting value, t h : h sync cycle, bc27: bit 7 of block control register 2) notes 1: set values fit for the following condition: wn1 < wn2. 2: when oc21 of osd control register 2 is ?0?, t h is 1 h sync . and when ?1?, t h is 2 h sync .
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 122 of 139 rej03b0128-0100z address 00d9 16 address 00d8 16 b7 b6 b5 b4 b3 b2 b1 b0 raster color register (rc) [address 00d9 16 ] b name functions after reset r w raster color register 0r aster color r control bit (rc0) 0 : no output 1 : output 0 1 raster color g control bit (rc1) 0 : no output 1 : output 0 2 0 : no output 1 : output 0 0 raster color b control bit (rc2) rw rw rw rw 3 0 : no output 1 : output raster color out control bit (rc3) 7 fix these bits to ?0.? 0 rw 0r w 00 0 po rt function selection bit (rc7) 0 : x cin , x cout 1 : p2 6 , p2 7 4 to 6 0 0 : at even field at odd field 1 : at even field at odd field b7 b6 b5 b4 b3 b2 b1 b0 i/o polarity control register (pc) [address 00d8 16 ] bn ame functions after reset r w i/o polarity control register 0h sync input polarity switch bit (pc0) 0 : positive polarity input 1 : negative polarity input 0 1 0 : positive polarity input 1 : negative polarity input 0 2r , g, b output polarity switch bit (pc2) 0 : positive polarity output 1 : negative polarity output 0 3 out1 output polarity switch bit (pc3) 0 : positive polarity output 1 : negative polarity output 0 5d isplay dot line selection bit (pc5) (see note) 0 6 field determination flag (pc6) 0 : even field 1 : odd field 1 4, 7 0 v sync input polarity switch bit (pc1) rw rw rw rw rw r rw fix these bits to 0. note: refer to the corresponding figure. 8.11.15 0
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 123 of 139 rej03b0128-0100z address 00db 16 address 00dc 16 b7 b6 b5 b4 b3 b2 b1 b 0 0 0: 1h sync (normal scan) 1: 2h sync (by scan) 1 vertical start position count selection bit (oc21) 2 fix this bit to "0." 3 nothing is assigned. this bit is write disable bit. when this bit is read out, the value is "0." 4 0 0 0 0 nothing is assigned. this bit is write disable bit. when this bit is read out, the value is "0." fix these bits to "0." 0 5 to 7 0: counts one time by 1h sync . (normal scan) 1: counts two time by 1h sync . (by scan) 00 0 0 osd control register (oc2) [address 00db 16 ] osd control register 2 inderterminate vertical character dot size (oc20) b name functions after reset r w r w r w r w r w r ? ? ? b7 b6 b5 b4 b3 b2 b1 b0 interrupt input polarity register (re) [address 00dc 16 ] b name functions after reset r w interrupt input polarity register int1 polarity switch bit (int1) 0 0 0 0 : positive polarity 1 : negative polarity 0 1 0 : positive polarity 1 : negative polarity 2 3 to 7 int2 polarity switch bit (int2) int3 polarity switch bit (int3) nothing is assigned. these bits are write disable bits. when these bits are read out, the values are ?0.? 0rw rw rw r? 0 : positive polarity 1 : negative polarity
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 124 of 139 rej03b0128-0100z b 7b 6b 5b 4b 3b 2b 1b 0 d a t a s l i c e r c o n t r o l r e g i s t e r 1 ( d s c 1 ) [ a d d r e s s 0 0 e 0 1 6 ] d a t a s l i c e r c o n t r o l r e g i s t e r 1 00 rw 0rw 2r e f e r e n c e c l o c k s o u r c e s e l e c t i o n b i t ( d s c 1 2 ) 0 : v i d e o s i g n a l 1 : h s y n c s i g n a l 0r w 0rw 0rw 11 0 : s t o p p e d 1 : o p e r a t i n g d a t a s l i c e r a n d t i m i n g s i g n a l g e n e r a t i n g c i r c u i t c o n t r o l b i t ( d s c 1 0 ) f i x t h e s e b i t s t o ? 0 . ? 3 , 4 000 10 : f 2 1 : f 1 s e l e c t i o n b i t o f d a t a s l i c e r e f e r e n c e v o l t a g e g e n e r a t i n g f i e l d ( d s c 1 1 ) f i x t h e s e b i t s t o ? 1 . ? 5 , 6 d e f i n i t i o n o f f i e l d s 1 ( f 1 ) a n d 2 ( f 2 ) h s e p v s e p f 1 : h s e p v s e p f 2 : b a f t e r r e s e t r w n a m ef u n c t i o n s 0rw f i x t h i s b i t t o ? 0 . ? 7 address 00e0 16
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 125 of 139 rej03b0128-0100z b7 b6 b5 b4 b3 b2 b1 b0 data slicer control register 2 (dsc2) [address 00e1 16 ] rw data slicer control register 2 indeterminate indeterminate indeterminate indeterminate indeterminate r? 1 0 r w r ? r ? 01 0: data is not latched yet and a clock-run-in is not determined. 1: data is latched and a clock-run-in is determined. caption data latch completion flag 1 (dsc20) fix this bit to ?1.? 2 read-only test bit 00: f2 1: f1 field determination flag(dsc23) 0: method (1) 1: method (2) vertical synchronous signal (v sep ) generating method selection bit (dsc24) 0 rw 50 : match 1: mismatch v-pulse shape determination flag (dsc25) r? 6 4 0 r w fix this bit to ?0.? b 1 after reset functions name definition of fields 1 (f1) and 2 (f2) h sep v sep f1: h sep v se p f2 : r ? 7 read-only test bit address 00e4 16 address 00e1 16 b7 b6 b5 b4 b3 b2 b1 b0 clock run-in detect register (crd) [address 00e4 16 ] r w clock run-in detect register 0 to 2 0 r? test bits 3 to 7 number of reference clocks to be counted in one clock run-in pulse period. clock run-in detection bit(crd3 to crd7) 0 r? read-only after reset functions nam be
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 126 of 139 rej03b0128-0100z b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 d ata c l oc k pos i t i on reg i ster (d ps) [add re ss 00 e 5 16 ] d a t a c l o c k p o s i t i o n r e g i s t e r 01 r w fi x t hi s bi t to ?0.? 1 fi x t hi s bi t to ?1.? 0 r w 10 0 b a f t e r r e s e t f u n c t i o n s n a m e r w 3 d ata c l oc k pos i t i on set bits (dps3 to dps7) 1 r w 4 to 7 0 2 fi x t hi s bi t to ?0.? 0 r w b7 b6 b5 b4 b3 b2 b1 b0 caption position register (cps) [address 00e6 16 ] caption position registe r 0 to 4 0 r w 0 r w caption position bits(cps0 to cps4) 6, 7 refer to the corresponding table (table 8.10.1). slice line mode specification bits (in 1 field) (cps6, cps7) 5 0: data is not latched yet and a clock-run-in is not determined. 1: data is latched and a clock-run-in is determined. caption data latch completion flag 2 (cps5) indeterminate r ? after reset functions na b m e r w address 00e5 16 address 00e6 16 address 00e9 16 b7 b6 b5 b4 b3 b2 b1 b0 sync pulse counter register (hc) [address 00e9 16 ] r w sync pulse counter register 0 to 4 0r 0r ? ? 6, 7 count value (hc0 to hc4) 5 0rw count source (hc5) 0: h sync signal 1: composite sync signal b after reset functions name nothing is assigned. these bits are write disable bits. when these bits are read out, the values are ?0.?
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 127 of 139 rej03b0128-0100z b7 b6 b5 b4 b3 b2 b1 b0 serial i/o mode register (sm) [address 00eb 16 ] b name functions after reset rw serial i/o mode register 0, 1 internal synchronous clock selection bits (sm0, sm1) b1 b0 0 0: f(x in )/8 or f(x cin )/8 0 1: f(x in )/16 or f(x cin )/16 1 0: f(x in )/32 or f(x cin )/32 1 1: f(x in )/64 or f(x cin )/64 2 synchronous clock selection bit (sm2) 3 port function selection bit (sm3) 4 5 tr ansfer direction selection bit (sm5) 0 0: p2 0 , p2 1 1: s clk , s out 0: external clock 1: internal clock 0: lsb first 1: msb first 6 fix this bit to ?0.? 0 0 0 0 0 0 transf er clock input pin selection bit (sm6) 0: input signal from s in pin 1: input signal from s out pin rw rw rw r w rw rw 0 7 fix this bit to ?0.? 0r w address 00eb 16 b7 b6 b5 b4 b3 b2 b1 b0 a-d control register 1 (ad1) [address 00ec 16 ] b after reset rw a-d control register 1 0 to 2 analog input pin selection bits (adc10 to adc12) name functions b2 b1 b0 0 0 0 : ad1 0 0 1 : ad2 0 1 0 : ad3 0 1 1 : ad4 1 0 0 : ad5 1 0 1 : ad6 ad7 ad8 1 1 0 : 1 1 1 : 4 storage bit of comparison result (adc14) 0: input voltage < reference voltage 1: input voltage > reference voltage 0 indeterminate 0 3t his bit is a write disable bit. when this bit is read out, the value is ?0.? rw r ? r ? 0 5 to 7 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are ?0.? r ? address 00ec 16
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 128 of 139 rej03b0128-0100z b7 b6 b5 b4 b3 b2 b1 b0 a-d control register 2 (ad2) [address 00ed 16 ] b after reset r w a-d control register 2 0 to 6 7 0 0 name functions d-a converter set bits (adc20 to adc25) b0 b1 b2 b3 b4 b5 nothing is assigned. this bit is a write disable bit. when these bits are reed out, the values are ? 0.? 1 000000 00000 0 0000 0 0 111 1 1 11111 1 1 b6 1 0 0 0 1 1 1111 1 rw r? : 3/256vcc : 5/256vcc : 251/256vcc : 253/256vcc : 255/256vcc : 1/256vcc address 00ed 16 address 00f4 16 b7 b6 b5 b4 b3 b2 b1 b0 timer mode register 1 (tm1) [address 00f4 16 ] b after reset w timer mode register 1 0 1 2 3 4 name functions timer 1 count source selection bit 1 (tm10) 0: f(x in )/16 or f(x cin )/16 (see note) 1: count source selected by bit 5 of tm 1 timer 2 count source selection bit 1 (tm11) 0: count source selected by bit 4 of tm1 1: external clock from tim2 pin timer 1 count stop bit (tm12) 0: count start 1: count stop timer 2 count stop bit (tm13) 0: count start 1: count stop timer 2 count source selection bit 2 (tm14) r 0 0 0 0 0 w r w r w r w r w r 0: f(x in )/16 or f(x cin )/16 (see note) 1: timer 1 overflow 5 timer 1 count source selection bit 2 (tm15) 0: f(x in )/4096 or f(x cin )/4096 (see note) 1: external clock from tim2 pin 0w r 6 timer 5 count source selection bit 2 (tm16) 0: timer 2 overflow 1: timer 4 overflow 0w r 7 timer 6 internal count source selection bit (tm17) 0w r 0: f(x in )/16 or f(x cin )/16 (see note) 1: timer 5 overflow note: either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register.
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 129 of 139 rej03b0128-0100z address 00f5 16 address 00f6 16 b7 b6 b5 b4 b3 b2 b1 b0 i 2 c data shift register 1(s0) [address 00f6 16 ] after reset functions name b w r w r i 2 c data shift register 0 to 7 this is an 8-bit shift register to store receive data and write transmit data. indeterminate note : to write data into the i 2 c data shift register after setting the mst bit to ?0? (slave mode), keep an interval of 8 machine cycles or more. d0 to d7 b6 b5 b4 b3 b2 b1 b0 timer mode register 2 (tm2) [address 00f5 16 ] b after reset rw 0 name functions timer 3 count source selection bit (tm20) 0 rw 1, 4 timer 4 count source selection bits (tm21, tm24) 0r w 2 3 0 timer 3 count stop bit (tm22) 0: count start 1: count stop timer 4 count stop bit (tm23) 0: count start 1: count stop 0 0 5 timer 5 count stop bit (tm25) 0: count start 1: count stop 0 6 timer 6 count stop bit (tm26) 0: count start 1: count stop 0 rw rw rw rw rw 7 timer 5 count source selection bit 1 (tm27) 0: f(x in )/16 or f(x cin )/16 (see note) 1: count source selected by bit 6 of tm1 b0 00 : f(x in )/16 or f(x cin )/16 (see note) 10 : f(x cin ) 01 : 11 : (b6 at address 00c7 16 ) external clock from tim3 pin b4 b1 00 : timer 3 overflow signal 01 : f(x in )/16 or f(x cin )/16 (see note) 10 : f(x in )/2 or f(x cin )/2 (see note) 11 : f(x cin ) note: either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. b7 timer mode register 2
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 130 of 139 rej03b0128-0100z b7 b6 b5 b4 b3 b2 b1 b0 0 b name functions after reset rw read/write bit (rbw) 1 to 7 slave address (sad0 to sad6) the last significant bit of address data is compared. 0: wait the first byte of slave address after start condition (read state) 1: wait the first byte of slave address after restart condition (write state) the address data is compared. i 2 c address register i 2 c address register (s0d) [address 00f7 16 ] 0 0 r? rw b 7 b3 b2 b 1 b0 i 2 c status re g ister ( s 1) [address 00f8 16 ] i 2 r 0 3 4 5 6, 7 b7 b6 0 0 : slave recieve mode 0 1 : slave transmit mode 1 0 : master recieve mode 1 1 : master transmit mode 1 2 0 0 0 1 0 b name functions after reset communication mode specification bits (trx, mst) 0 : bus free 1 : bus busy bus busy flag (bb) 0 : interrupt request issued 1 : no interrupt request issued i 2 c-bus interface interrupt request bit (pin) 0 : not detected 1 : detected arbitration lost detecting flag (al) (see note) 0 : address mismatch 1 : address match slave address comparison flag (aas) (see note) 0 : no general call detected 1 : general call detected general call detecting flag (ad0) (see note) 0 : last bit = ?0 ? 1 : last bit = ?1 ? last receive bit (lrb) (see note) note : these bits and flags can be read out, but cannnot be written. indeterminate 0 w r r ? r? r? r? rw rw rw (see note) (see note) (see note) (see note) address 00f7 16 address 00f8 16
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 131 of 139 rej03b0128-0100z b7 b6 b5 b4 b3 b2 b1 b0 0 to 2 bit counter (number of transmit/recieve bits) (bc0 to bc2 ) b2 b1 b0 0 0 0 : 8 0 0 1 : 7 0 1 0 : 6 0 1 1 : 5 1 0 0 : 4 1 0 1 : 3 1 1 0 : 2 1 1 1 : 1 3i 2 c-bus interface use enable bit (eso) 0: disabled 1: enabled 4d ata format selection bit(als) 0: addre ssing mode 1: free data format 5a ddressing format selection bit (10bit sad) 0: 7- bit addressing format 1: 10-bit addressing format 6, 7 connection control bits between i 2 c-bus interface and ports (bsel0, bsel1) b7 b6 connection port (see note) 0 0: none 0 1: scl1, sda1 1 0: scl2, sda2 1 1: scl1, sda1 0 0 0 0 0 i 2 c control register (s1d) [address 00f9 16 ] i 2 c control register b name function s after reset r w note: set the corresponding direction register to "1" to use the port as multi-master i 2 c-bus interface. to use scl1, sda1, scl2 and sda2, set the port p3 register (address 00c6 16 ) bit 2 to 0. r w r w r w r w r w scl2, sda2 address 00f9 16
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 132 of 139 rej03b0128-0100z address 00fa 16 b7 b6 b5 b4 b3 b2 b1 b0 i 2 c clock control register (s2) [address 00fa 16 ] i 2 c clock control register 0 to 4 scl frequency control bits (ccr0 to ccr4) 7 5 6 scl mode specification bit (fast mode) 0: standard clock mode 1: high-speed clock mode 0 standard clock mode functions name after reset rw b 0 0 0 ack bit (ack bit) ack clock bit (ack) 0: ack is returned. 1: ack is not returned. 0: no ack clock 1: ack clock high speed clock mode setup disabled setup disabled 00 to 02 setup disabled 333 03 setup disabled 250 04 100 400 (see note) 05 83.3 166 06 500/ccr value 1000/ccr value ... 17.2 34.5 1d 16.6 33.3 1e 16.1 32.3 1f ( = at 4 mhz, unit : khz) notes 1. at 400khz in the high-speed clock mode, the duty is as below . ?0? period : ?1? period = 3 : 2 in the other cases, the duty is as below. ?0? period : ?1? period = 1 : 1 2. at fscin = 3.58 mhz, = 8.95/2 mhz at fscin = 4.43 mhz, = 8.86/2 mhz values shown in table is as below : at fscin = 3.58 mhz, each value ? 8.95/8 at fscin = 4.43 mhz, each value ? 8.86/8 setup value of ccr4? ccr0 rw rw rw rw
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 133 of 139 rej03b0128-0100z b7 b6 b5 b4 b3 b2 b1 b0 interrupt request register 1 (ireq1) [address 00fc 16 ] w r interrupt request register 1 0 b name functions afrer reset 0 : no interrupt request issued 1 : interrupt request issued timer 1 interrupt request bit (tm1r) 1 timer 2 interrupt request bit (tm2r) 2 timer 3 interrupt request bit (tm3r) 3t imer 4 interrupt request bit (tm4r) 4 osd interrupt request bit (osdr) 5 vsync interrupt request bit (vscr) 6 int3 external interrupt request bit (in3r) 7 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 0 0 0 0 0 0 0 ? : ?0? can be set by software, but ?1? cannot be set. ? ? r ? r ? r ? r ? r ? r ? r r nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is ?0.? b7 b6 b5 b4 b3 b2 b1 b0 after reset rw cpu mode register 0, 1 2 3, 4 0 1 name functions processor mode bits (cm0, cm1) 0 0: single-chip mode 0 1: 1 0: not available 1 1: fix these bits to ?1.? 1 stack page selection bit (cm2) (see note1) 1 b1 b0 0: 0 page 1: 1 page 1 0 0 5 1 6 0 main clock (x in ) stop bit (cm6) cpu mode register (cm) [address 00fb 16 ] r w rw r w r w rw x cout drivability selection bit (cm5) 0: low drive 1: high drive 0: oscillatin g 1: stopped 7 0 internal system clock selection bit (cm7) (see note2) rw 0: x in selected (high-speed mode) 1: x cin ?x cout selected or fscin input selected (low-speed mode) note 1: this bit is set to ?1? after the reset release. 2: x cin -x cout and fscin are switched over using clock control register 2 (address 0211 16 ) bit 2. b address 00fb 16 address 00fc 16
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 134 of 139 rej03b0128-0100z b7 b6 b5 b4 b3 b2 b1 b0 interrupt request register 2 (ireq2) [address 00fd 16 ] after reset rw interrupt request register 2 0 b int1 external interrupt name functions request bit (in1r) 0 : no interrupt request issued 1 : interrupt request issued 1 data slicer interrupt request bit (dsr ) 2 serial i/o interrupt request bit (sir) 3 4 int2 external interrupt request bit (in2r) 5 7f ix this bit to ?0.? 0 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 ? : ?0? can be set by software, but ?1? cannot be set. 0 0 ? 0 0 ? 0 ? 0 ? 0 : no interrupt request issued 1 : interrupt request issued r r r r ? r r ? rw f(x in )/4096 interrupt request bit (ckr) 0 : no interrupt request issued 1 : interrupt request issued multi-master i 2 c-bus interrupt request bit (iicr) 0 : no interrupt request issued 1 : interrupt request issued 6t imer 5 6 interrupt request bit (tm56r) 0 : no interrupt request issued 1 : interrupt request issued 0 ? r b7 b6 b5 b4 b3 b2 b1 b0 interrupt control register 1 (icon1) [address 00fe 16 ] b name after reset function s rw interrupt control register 1 0 timer 1 interrupt enable bit (tm1e) 0 : interrupt disabled 1 : interrupt enabled 1 timer 2 interrupt enable bit (tm2e) 2 timer 3 interrupt enable bit (tm3e ) 3 4 osd interrupt enable bit (osde) 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 0 0 0 0 0 rw rw rw rw rw r? 7 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is ?0.? timer 4 interrupt enable bit (tm4e) 0 : interrupt disabled 1 : interrupt enabled 5 v sync interrupt enable bit (vsce) 0 : interrupt disabled 1 : interrupt enabled 0 rw 6 int3 external interrupt enable bit (in3e) 0 : interrupt disabled 1 : interrupt enabled 0 rw address 00fd 16 address 00fe 16
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 135 of 139 rej03b0128-0100z b7 b6 b5 b4 b3 b2 b1 b0 interrupt control register 2 (icon2) [address 00ff 16 ] b name function s after reset rw interrupt control register 2 0 int1 external interrupt enable bit (in1e) 0 : interrupt disabled 1 : interrupt enabled 1 data slicer interrupt enable bit (dse) 2 serial i/o interrupt enable bit (sie) 3 4 int2 external interrupt enable bit (in2e) 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 0 0 0rw rw rw rw 0rw f(x in )/4096 interrupt enable bit (cke) 0 : interrupt disabled 1 : interrupt enabled 5 multi-master i 2 c-bus interface interrupt enable bit (iice) 0 : interrupt disabled 1 : interrupt enabled 6 timer 5 6 interrupt enable bit (tm56e ) 0 : interrupt disabled 1 : interrupt enabled 7 timer 5 6 interrupt switch bit (tm56c) 0 : timer 5 1 : timer 6 0rw 0rw 0rw b 7 b6 b 5 b 4 b 3 b 2 b 1 b 0 pwm mode register 1 (pm1) [address 0208 16 ] b a f t e r r e s e t rw p w m m o d e r e g i s t e r 1 0 1 , 2 3 0 n a m ef unctions p w m o u t p u t p o l a r i t y s e l e c t i o n b i t ( p m 1 3 ) i n d e t e r m i n a t e 0 n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e ? 0 . ? 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y r w r ? rw p w m c o u n t s s o u r c e s e l e c t i o n b i t ( p m 1 0 ) 0 : c o u n t s o u r c e s u p p l y 1 : c o u n t s o u r c e s t o p 4 t o 7 i n d e t e r m i n a t e n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e ? 0 . ? r ? address 00ff 16 address 0208 16
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 136 of 139 rej03b0128-0100z b7 b6 b5 b4 b3 b2 b1 b0 pwm mode register 2 (pm2) [address 0209 16 ] b after reset r w pwm mode register 2 0 1 2 3 4 0 name functions p0 0 /pwm0 output selection bit (pm20) 0 : p0 0 output 1 : pwm0 output p0 2 /pwm2 output selection bit (pm22) 0 : p0 2 output 1 : pwm2 output p0 3 /pwm3 output selection bit (pm23) 0 : p0 3 output 1 : pwm3 output p0 4 /pwm4 output selection bit (pm24) 0 : p0 4 output 1 : pwm4 output 5 to 7 fix these bits to ?0.? p0 1 /pwm1 output selection bit (pm21) 0 : p0 1 output 1 : pwm1 output 0 0 0 0 0 rw rw rw rw rw rw 00 0 b7 b6 b5 b4 b3 b2 b1 b0 rom correction enable register (rcr) [address 020e 16 ] b after reset rw rom correction enable register 0 vector 1 enable bit (rc0) name functions 0: disabled 1: enabled 1 vector 2 enable bit (rc1) 0: disabled 1: enabled 2 to 7 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are ?0.? 0 0 0 rw rw r? address 0209 16 address 020e 16
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 137 of 139 rej03b0128-0100z address 0210 16 clock frequency set register(cfs) [address 0210 16 ] clock frequency set register 0 to 7 b7 b6 b5 b4 b3 b2 b1 b0 clock frequency bit (cfs 0 to 7) 0e fscin=3.58mhz fscin=3.58mhz fscin=4.43mhz 0e 8.95 26.85 fscin=4.43mhz 0b 8.86 26.58 main clock frequency f(x in ) [ mhz ] reference clock input setting value set to 0e 16 set to 0b 16 osd clock frequency f( osc ) [ mhz ] name b functions after reset r w r w note: do not set other than the values shown above to cfs. address 0211 16 4 to 7 b7 b6 b5 b4 b3 b2 b1 b0 0 w r 0: fscin input signal 1: x cin -xco ut 0 w r 0 w r 2 00001 0 0 note: this bit is valid when the cpu mode register (address 00fb 16 ) bit 7 (cm7) is set to 1. 3 0 w r fix these bits to "0" fix these bits to "0" fix this bit to "1" clock control register 2 (cc2) [address 0211 16 ] name b functions after reset r w 0,1 clock sauce switch bit (note) (cc22) clock control register 2
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 138 of 139 rej03b0128-0100z address 0212 16 5 0 to 4 r,g,b,out output amplitude level selection bit (cc35) b7 b6 b5 b4 b3 b2 b1 b0 0 w r 0 w r 6 0 w r 7 (cc37) 0: clock control signal 1: p1 0 i/o 0 w r 0 0 0 0 0 0 fix these bits to "0" fix this bit to "0" clock control register 3 (cc3) [address 0212 16 ] name b functions after reset r w clock control register 3 0: 0v?v cc 1: 0v?about 0.6v cc p1 0 function-selection bit (note) note: when used as the clock control signal, set the port 1 direction register (address 00c3 16 ) bit 0 to 1.
m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP rev.1.00 nov 01, 2002 page 139 of 139 rej03b0128-0100z 19. package outline ssop42-p-450-0.80 w eight(g) ? jedec code 0.63 eiaj package code lead material alloy 42 42p2r-a/e plastic 42pin 450mil ssop symbol min nom max a a 2 b c d e l l 1 y dimension in millimeters h e a 1 i 2 ? ? .25 0 .05 0 .13 0 .3 17 .2 8 ? .63 11 .3 0 ? ? ? .27 1 ? ? .0 2 .3 0 .15 0 .5 17 .4 8 .8 0 .93 11 .5 0 .765 1 ? .43 11 ? ? .4 2 ? .4 0 .2 0 .7 17 .6 8 ? .23 12 .7 0 ? .15 0 ? b 2 ?.5 0? ? 0 ?10 e e 1 42 22 21 1 h e e d e y f a a 2 a 1 l 1 l c e b 2 e 1 i 2 recommended mount pad detail f z z 1 detail g ? ? z 1 0.75 ? ? 0.9 z b g
revision history rev. date description page summary m37150m6/m8/ma/mc/mf-xxxfp, M37150EFFP 1.00 nov 01, 2002 first edition issued a - 1
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